Symphony EDA (R) VHDL Compiler/Simulator Module VhdlP, Version 2.3, Build#8.
Copyright(C) Symphony EDA 1997-2004. All rights reserved.
Reading C:\Program Files\Symphony EDA\VHDL Simili 2.3\bin\symphony.ini ...
Library 'ieee'		==> $SYMPHONYEDA/lib/ieee/ieee.sym (readonly)
Library 'c'		==> c.sym
Library 'work'		==> Library 'c' ==> c.sym
Reading  $SYMPHONYEDA\lib\ieee\ieee.sym\std_logic_1164\prim.var
Parsing Package:ctype_h @ line ..\..\ctype_h.vhd:28
Writing  c.sym\ctype_h\prim.var
Parsing Package Body:ctype_h @ line ..\..\ctype_h.vhd:69
Writing  c.sym\ctype_h\_body.var
Elapsed Time: 00h:00m:00s:040ms
 Kernel Time: 00h:00m:00s:140ms
   User Time: 00h:00m:00s:070ms
Symphony EDA (R) VHDL Compiler/Simulator Module VhdlP, Version 2.3, Build#8.
Copyright(C) Symphony EDA 1997-2004. All rights reserved.
Reading C:\Program Files\Symphony EDA\VHDL Simili 2.3\bin\symphony.ini ...
Library 'ieee'		==> $SYMPHONYEDA/lib/ieee/ieee.sym (readonly)
Library 'c'		==> c.sym
Library 'work'		==> Library 'c' ==> c.sym
Parsing Package:strings_h @ line ..\..\strings_h.vhd:35
Writing  c.sym\strings_h\prim.var
Parsing Package Body:strings_h @ line ..\..\strings_h.vhd:65
Writing  c.sym\strings_h\_body.var
Elapsed Time: 00h:00m:00s:040ms
 Kernel Time: 00h:00m:00s:130ms
   User Time: 00h:00m:00s:080ms
Symphony EDA (R) VHDL Compiler/Simulator Module VhdlP, Version 2.3, Build#8.
Copyright(C) Symphony EDA 1997-2004. All rights reserved.
Reading C:\Program Files\Symphony EDA\VHDL Simili 2.3\bin\symphony.ini ...
Library 'ieee'		==> $SYMPHONYEDA/lib/ieee/ieee.sym (readonly)
Library 'c'		==> c.sym
Library 'work'		==> Library 'c' ==> c.sym
Parsing Package:debugio_h @ line ..\..\debugio_h.vhd:26
Writing  c.sym\debugio_h\prim.var
Parsing Package Body:debugio_h @ line ..\..\debugio_h.vhd:39
Writing  c.sym\debugio_h\_body.var
Elapsed Time: 00h:00m:00s:100ms
 Kernel Time: 00h:00m:00s:130ms
   User Time: 00h:00m:00s:080ms
Symphony EDA (R) VHDL Compiler/Simulator Module VhdlP, Version 2.3, Build#8.
Copyright(C) Symphony EDA 1997-2004. All rights reserved.
Reading C:\Program Files\Symphony EDA\VHDL Simili 2.3\bin\symphony.ini ...
Library 'ieee'		==> $SYMPHONYEDA/lib/ieee/ieee.sym (readonly)
Library 'c'		==> c.sym
Library 'work'		==> Library 'c' ==> c.sym
Reading  c.sym\ctype_h\prim.var
Reading  $SYMPHONYEDA\lib\ieee\ieee.sym\std_logic_1164\prim.var
Parsing Package:stdlib_h @ line ..\..\stdlib_h.vhd:25
Writing  c.sym\stdlib_h\prim.var
Parsing Package Body:stdlib_h @ line ..\..\stdlib_h.vhd:48
Writing  c.sym\stdlib_h\_body.var
Elapsed Time: 00h:00m:00s:040ms
 Kernel Time: 00h:00m:00s:140ms
   User Time: 00h:00m:00s:070ms
Symphony EDA (R) VHDL Compiler/Simulator Module VhdlP, Version 2.3, Build#8.
Copyright(C) Symphony EDA 1997-2004. All rights reserved.
Reading C:\Program Files\Symphony EDA\VHDL Simili 2.3\bin\symphony.ini ...
Library 'ieee'		==> $SYMPHONYEDA/lib/ieee/ieee.sym (readonly)
Library 'work'		==> work.sym
Library 'c'		==> c.sym
Reading  c.sym\stdlib_h\prim.var
Reading  c.sym\ctype_h\prim.var
Reading  $SYMPHONYEDA\lib\ieee\ieee.sym\std_logic_1164\prim.var
Parsing Entity:stdlib_h_test @ line ..\..\..\test\stdlib_h_test.vhd:29
Writing  work.sym\stdlib_h_test\prim.var
Parsing Architecture:stdlib_h_test(stdlib_h_test_arch) @ line ..\..\..\test\stdlib_h_test.vhd:31
Writing  work.sym\stdlib_h_test\_stdlib_h_test_arch.var
Parsing Configuration:stdlib_h_test_cfg @ line ..\..\..\test\stdlib_h_test.vhd:100
Writing  work.sym\stdlib_h_test_cfg\prim.var
Elapsed Time: 00h:00m:00s:050ms
 Kernel Time: 00h:00m:00s:150ms
   User Time: 00h:00m:00s:070ms
Symphony EDA (R) VHDL Compiler/Simulator Module VhdlE, Version 2.3, Build#8.
Copyright(C) Symphony EDA 1997-2004. All rights reserved.
Note: CSVHE0051: vhdle: Thank you for using the free version of  from VHDL Simili.
Warning: CSVHE0055: vhdle: Simulator will run at reduced perfomance and with certian features disabled
Reading C:\Program Files\Symphony EDA\VHDL Simili 2.3\bin\symphony.ini ...
Library 'ieee'		==> $SYMPHONYEDA/lib/ieee/ieee.sym (readonly)
Library 'work'		==> work.sym
Reading  work.sym\stdlib_h_test_cfg\prim.var
Reading  work.sym\stdlib_h_test\_stdlib_h_test_arch.var
Library 'c'		==> c.sym
Reading  c.sym\stdlib_h\_body.var
Reading  c.sym\ctype_h\_body.var
Reading  $SYMPHONYEDA\lib\ieee\ieee.sym\std_logic_1164\_body.var
	# of Signals       = 0
	# of Components    = 0
	# of Processes     = 1
	# of Drivers       = 0
Design Load/Elaboration Elapsed Time: 00h:00m:00s:040ms
--begin test;
hello, world: stdlib_h_test
strtoul base=10 123=123 endptr= 4=4
Time: 0 ps+0
strtoul base=8   64=83 endptr= 4=4
strtoul base=16 291=291 endptr= 4=4
strtoul base=16 291=291 endptr= 4=4
strtoul base=0  123=123 endptr= 4=4
strtoul base=0   83=83 endptr= 5=5
strtoul base=0  291=291 endptr= 6=6
strtoul base=0  291=291 endptr= 6=6
atoi    base=10 123=123
atoi    base=10 -123=-123
atoi    base=10 +123=123
--end test;
Simulation stopped at: 0 ps
Simulation Elapsed Time: 00h:00m:00s:000ms
Total Kernel Time: 00h:00m:00s:190ms
  Total User Time: 00h:00m:00s:120ms