Synopsys 1076 VHDL Simulator Version 2000.12 -- Dec 26, 2000 Copyright (c) 1990-2000 by Synopsys, Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys, Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. --begin test; %+ #-0.0s :: 0.0s :: 10s :hello, world: 10.0s : : .10s :hello, wor: 0.10s :hello, wor: -10s :hello, world: -10.0s : : .15s :hello, world: 0.15s :hello, world: -15s :hello, world : -15.0s : : 15.10s : hello, wor: -15.10s :hello, wor : -5.10s :hello, wor : true=1 false=0 bit=1 b1=00110101 b2=01010011 vu1=0LWXU1Z- v1=0LWXU1Z- v2=0LWXU1Z- std_logic=1 std_ulogic=0 -15 =:10001: -1 =:11: -1 =:-1: s -7=:1001: u -7=:9: d -7=:-7: +15 =:11110: d =:15: #3d =:1945: 3d =: 1945: +3d =:+1945: + 3d =:+1945: +3d =:+1945: 3d =:1945: 3d =:-1945: 10x =: e99: 10x =: 16e: 10x =: 0xe99: 10x =: 0x16e: -1945=:111001100001: 10d =: 1945: 10d =: -1945: 010d =:0000001945: 010d =:-000001945: 010d=:0000001945: 010d=:-000001945: +010d=:+000001945: +010d=:-000001945: s =:10011001111: 10s =:10011001111: d =:-103: 10d =: -103: --end test; (vhdlsim): Simulation complete, time is 0 NS.