Synopsys 1076 VHDL Simulator Version 2000.12 -- Dec 26, 2000

	        Copyright (c) 1990-2000 by Synopsys, Inc.
	                    ALL RIGHTS RESERVED
	This program is proprietary and confidential information
	of  Synopsys, Inc. and may be used and disclosed only as
	authorized in a  license agreement  controlling such use
	and disclosure.


--begin test;
hello, world: strings_h_test
strlen('abcde'): 5==5
strlen('abcde'+4): 2==2
strlen('123'): 3==3
strcpy(s, ''): []==[]
abcdefgh==abcdefgh
abc1234==abc1234
cdefgh==cdefgh
ab_CDE==ab_CDE
strcat: abcd123==abcd123
strcat: abcd23==abcd23
strcat: 123==123
s[2..$]=ello, world
strlen('lo, world'): 9==9
s[2..$]='lo, world'==lo, world
s[2..$]='wo'==wo
s[2..$]='hexyz'==hexyz
--end test;
(vhdlsim): Simulation complete, time is 0 NS.