Frequently Asked Questions

About Using UNIX

Q: I got "/u/../.xinitrc not found" when I startx.
A:
You need to put a file called .xinitrc in your home directory.

Q: I have .xinitrc file in my home directory, but I still got "/u/../.xinitrc:x11emacs not found" error when I startx.
A:
If you copy the file .xinitrc from the place described in CWRU UNIX Cookbook, then most likely you'll have this kind of problem. The solution is to edit your .xinitrc file and remove x11emacs.

Q: I got "can't open display" error when I try to open a window on a remote machine.
A:
You forgot to set xhost and environment. The procedure is like this:

1. Suppose you currently login to papaya in UNIX lab.
2. Suppose you have two windows opened, A and B.
3. In window A, you remote login to, say, earth.
4. Go to window B, and type xhost + (A blank in between).
5. Then come back to window A, and type setenv DISPLAY papaya:0.0.

Q: The computer seems to hang there, or I got "... not responding..".
A:
The network is always the problem, be patient!

Q: I can login to any machine in the UNIX lab. But I can not login to the machines in the hardware lab. What's the scoop here?
A:
It is because the machines in 413 are under direct control of the professor. Nobody can login unless the professor put his/her login name in. Talk to the professor.

About VHDL

Q: I got "component not found" error when I debug my structural VHDL code with "COMPONENT" and "PORT MAP" statements.
A:
Two problems could happen:
1.Check if you put all those component files along with your "main" VHDL that uses them.
2.Check if you put all of them within the "main" VHDL file.
The bottomline is that you can only use one "architecture--begin--end" constrcut in any VHDL file. The way to do this is:

1.Suppose you have a counter VHDL called counter.vhd
2.Suppose you have pre-constructed several components like XOR.vhd , AND.vhd , or NOT.vhd
3.Suppose you want to "interconnect" them by using "PORT MAP" statement in this counter.vhd
4.The counter.vhd would look like:

component XOR
  PORT()
component AND
  PORT()
component NOT
  PORT()
  ...mumble, mumble...

--See, this is pretty much similar to a C/C++ program (nevertheless,
--VHDL is still a PROGRAM created by computer people with the same 
--thinking). You need to list the "functions" you pre-defined
--elsewhere with, of course, the argument lists... 

--now come the architecture thing

architecture
  PORT MAP(..mumble, mumble...)
end
   

Q: What does a sensitivity list do in VHDL ?
A:
Remember in VHDL, a process is a way to execute sequential statements. So you need some kind of stimulus outside the "process" to get it executed. These stimulus should be included in the sensitivity list. But there are exceptions. If the process includes one or more "wait" statements (clock), then the sensitivity list is optional.
So the guidline is :

A good practice is to put all primary inputs, including clock and reset, on the sensitivity list. It does not affect the final synthesis process. So no harm to the final circuit if you do so. You might want to do so when you see some error/warning messages like " this process will never execute a wait statement (no other processes will have a chance to run)". And you know your design is a combinational circuit, it does not need a clock.

About Setting Up and using SYNOPSYS

Q: I got "/u/../.. permission denied" error.
A:
Usually this kind of error comes from the conflict among different environmental settings. The best way to resolve this is:

1. Forget about set up the path in your .tcshrc file. Create a working directory for yourself, say, "synopsys".
2. Within the directory, create another sub-directory called "WORK". The name WORK is important here. SYNOPSYS will store all synthesized, compiled VHDL codes here. But it is not necessary to put your source VHDL codes in there. You always have the choice to specify the directory.
3. Create a file called "start_synop_xilinx", or whatever you want to call it. Here I just stick with this name.
4. Create another file ".synopsys_dc.setup". The name is important.
5. Put these two files in "synopsys", but not in "WORK".
6. Every time you want to run SYNOPSYS, type source start_synop_xilinx within "synopsys".
7. Then type dc_shell for command-line mode, design_analyzer & for graphical VHDL compiler, vhdldbx & for graphical VHDL debugger.
8. To get online manual for SYNOPSYS, just type synop_iview &.
9. To get online manual for XILINX, type acroread &.

Look for the manuals, quick-starts in this web site for more details.

Q: How do I compile and simulate the VHDL code ?
A:
OK. Suppose you have a piece of VHDL code called test1.vhd (it is a 3-bit counter counts from 0 to 7 and starts over from 0):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

--Define the I/O port--

ENTITY test1 IS
   PORT(
         clk     : IN BIT;
         reset   : IN BIT;
         count   : OUT INTEGER range 0 to 7
       );
END test1;

--define the body (behavior of the circuit)--

ARCHITECTURE my_arch OF test1 IS

--temperary "variable" to hold the value between clocks--
--this is pretty much like the temp variables you would--
--use in a C/C++ program                               --

  signal count_tmp : integer range 0 to 7;
begin
  process
  begin
    wait until (clk'event and clk='1');      --clocking--
    if reset = '1' or count_tmp = 7 then  --reset or start over--
      count_tmp <= 0;
    else
      count_tmp <= count_tmp + 1;        --increment the count--
    end if;
  end process;
  count <= count_tmp;                    --final output--
END my_arch;
     

In the directory with all other VHDL files, type in (%> is your shell prompt):

%>design_analyzer &
      

%>vhdldbx &
      

1.Add a variable into the trace list by highlighting the variable, say, clk by left click-and-drag the mouse with cursor on that variable.
2.Click the "trace" button in the lower window.
3.A trace window will show up. For the first selected variable, it takes some time.
4.Repeat these steps for all other variables you want to trace in the later simulation.
5.This is a counter example. We first set clk to 0 by clicking on "Stimulus" on the tool bar in the upper window. And select "Assign".
6.In the assign window, highlight '0' and click OK. Note that "assign ('0') clk" shows in the lower window.
7.Repeat this for other variables in the trace list (i.e. the variables in the left part of the trace window).
8.Type in the simulation period you want to perform in the "RUN" box in the lower window. Then click on "RUN". See the change in the trace window. Note that SYNOPSYS assigns integers instead of binaries for the "count" output here. This is because we use "integer" as the type for that variable. If we further decode the output into 3 bits, then it is another story... Every variable will be in binaries.
9.You can print out the trace diagram through the lab printer.

Q: OK. This is great. But I was clocking "clk" like crazy. Is there any easier way to do it ?
A:
You can write a test bench file to do all this and other routine works and put all your test schemes in a file. Check out the book "A VHDL Primer" listed in REFERENCE, chapter 11. Or you can go to this web site and see the format of a testbench file (Seg7TestBench.vhdl):

http://lenkkari.cs.tut.fi/~tuominen/FPGA/FPGA_Demo.html

Blibrary ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behav of testbench is
  signal clk, reset: bit :='0';
  signal count : integer :=0;

component test1
|  port(
        clk     : in bit;
        reset   : in bit;
        count   : out integer range 0 to 7
      );
end component;

begin
  test1A:test1
      port map(clk, reset, count);
  reset <= '1', '0' after 30 ns;
  clk <= not clk after 20 ns;
end behav;

configuration TBCfg of testbench is
   for Behav
      for test1A:test1
         use entity work.test1(MY_ARCH);
      end for;
   end for;
end TBCfg;
   

1.Do VHDL analyze for the original VHDL (test1.vhd).
2.Do VHDL analyze for this testbench VHDL (test1_TB.vhd). For this case, you'll see "Error....synthesis...". This is something to do with the final logic synthesis process. Since this is not the VHDL we'll use to synthesis, it's OK. Just ignore it and all other warning messages.
3.In VHDLDBX, call in the testbench file instead of | original VHDL. Double check it in the upper window. The file we need is "TBCFG" for this example.
4.In this case, we already set the initial values for the variables in the test bench. So we don't have to "assign" values again. But we DO need to include the variables in the trace list as explained above.
5.Set the running time to, say, 100. And click on "RUN". You should be able to see the change. The beauty is that you don't assign clk any more. You just keep clicking on "RUN".
6.You can also "overwrite" the variable values between RUNs. Just use the steps explained above in the previous question.
7.This testbench shows a simulation scheme of reseting at time 0, and un-reset after 30 ns. The clock period is 20 ns. The initial value for "count" is 0.

Q: How do I assign values to a BIT_VECTOR in VHDLDBX ?
A:
Try this! Suppose you want to assign value 1101 to A which is a BIT_VECTOR (0 TO 3) :

1.Still need to do all the analyze, VHDLDBX, add trace list stuff explained in the previous question.
2.In the bottom line box in the lower window (in VHDLDBX), type in assign "1101" A
3.Note that the test sequence matters here (from left to right or vice versa). Depends on you use (3 DOWNTO 0) or (0 TO 3).
4.Everything else should be pretty much the same as in the previous question.
5.Finally, note that SYNOPSYS uses HEX numbers to display the value in a bit vector. But you can click on the small arrow head to the left of the variable in the trace window to EXPAND the bit vector into individual bits. Each bit now has its own trace shown in binary number. Check it out!

Q: How do I "synthesize" a VHDL code into a circuit with logic gates ?
A:
Try the following steps

1.Make sure you don't have any error during the compilation
2.In the design analyzer window, click on "File" and select "Elaborate...". This will bring up another window.
3.Fill in the "library" and "design". "Library" means the directory your VHDL is in. And "design" means the code name.
4.Click on OK. After some time, you should be able to see a box in the design analyzer window.
5.Zoom in to the design by double clicking on the box. Repeat this until you can see the gates within.
6.You can print it out by FILE-->Plot.. The printer in the lab is "hpz".

About Using XILINX...

Q: How do I use the "make_everything" script ?
A:
Steps are:

1.Look at the script carefully. You need to create two new directories WORK (again!) and XILINX_SCRIPTS (as shown in the make_everything script). If you don't want to change the script, you can just follow the steps.
2.The directory hierarchy is like (* denotes executable, and / denotes directory):

current   -- WORK/ (should be empty at the beginning)
directory    XILINX_SCRIPTS/ --(all make_...in here except make_everything)
 ...         .synopsys_dc.setup (put a copy here)
             make_everything*
             hello.vhd (you can put your VHDL here)
             hello.cst
             ...
  

3.Modify your synopsys source file, and put this line:

setenv XILINX_SCRIPTS /u/your_login_name/.../XILINX_SCRIPTS
  

This tells SYNOPSYS where to find the sub-directory "XILINX_SCRIPTS".
Don't forget to source it once you are done.
4.Once you set up your directories, and put all needed files in the right place, change the mode of the scripts to executables. This can be done by: chmod 700 filename
Here the filename is all make_*. 700 means you set the mode of the file(s) to be executable, writable, and readable only by the owner.
5.Now you can type "make_everything" to run the process. The full command is (Use Michael's hello.vhd & hello.cst as examples): make_everything hello.vhd 4003apc84-6 "David" hello_world
*hello.vhd is the top level vhdl code in your design
*4003apc84-6 is the part number supported by SYNOPSYS/XILINX. The other two supported by CES/CWRU Lab are 3020pc68-70 and 3020apc68-7, depends on which chip on board you want to use.
*David is the author's name. (You should use your name).
*hello_world is the top-level entity name. (Check the sample codes by Michael, hello.vhd and hello.cst. And you will see the entity name.)

See the sample codes by Michael.

Q: Where can I find the documentation about downloading my design to the FPGA demonstration board ?
A:
Try the XILINX ftp site :

1.In any directory, type : ftp ftp.xilinx.com
2.At the NAME prompt, type anonymous
3.At the PASSWORD prompt, type in your full (UNIX) e-mail address. For example, li@alpha.ces.cwru.edu
4.You should be in the ftp prompt now.
5.At the ftp prompt, cd to this directory: /pub/documentation/xactstep6/
6.Type mget hardware.pdf
7.Type y after the message "mget hardware.pdf? "
8.When done, type bye or quit to exit FTP.
9.Start acrobat reader to read this pdf file by typing acroread &. Don't forget to source the SYNOPSYS/XILINX path file before you use acrobat reader. This is the online manual for the FPGA demo board. Pay attention to chapter 1 and chapter 3 for now.
10.There is a hard copy of this manual in the lab, named "Hardware & Peripherals User Guide".
11.Here are some pages you can't miss if you just want a quick-start...

Chapter 1:

  page 6 Board schematic
         So you know where the power cable goes to the board.
  pages 27-29 FPGA Demonstration Board Operation
         Forget about the PROM thing for now.
Chapter 3:

  pages 8-9 What you should do before using XChecker.
  ... 
   

Q: What is this "OSC4" thing ?
A:
"OSC4" is an on-chip, internal 5-frequency clock-signal generator. For now, it is available ONLY for XC4000 series FPGAs. It provides internal clock signals in applications where timing is not critical. The available frequencies are determined by FPGA device components, so they are process dependent. Therefore, the available frequencies vary from devices to devices. Nominal frequensies are 8Mhz, 500Khz, 16Khz, 490Hz, and 15Hz. Although there are 5 outputs, only three can be used at a time, with 8 Mhz on one output and one frequency each on any two of the remaining 4 outputs. An error occurs if more than 3 outputs are used at the same time. The internal circuit must be connected through buffers to OSC4 outputs. (From XILINX Development System--Libraries Guide, p 3-388. This guide can be found on the XILINX FTP site mentioned above.)

Q: How do I use this OSC4 in my VHDL design ?
A:
Here is an example:

library ieee;
use ieee.std_logic_1164.all;

entity OSC4TEST is
  port (
         DATA: in std_logic;
         OUTDATA: inout std_logic
       );
end OSC4TEST;

architecture OSC4_ARCH of OSC4TEST is
                    --declaire a component defined elsewhere--
  component OSC4    --this example only uses the 500Khz output--
    port (
           F500K: out std_logic   
           --for 8 MHZ, this is F8M, for 15Hz, it is F15--
         );
  end component;

  signal CLK: std_logic;  --an intermediate "node"--
  begin

    --this is the VHDL syntax to connect one "node" to another--
    U1: OSC4 port map (F500K => CLK);

    process (CLK)
    begin
      if (CLK'event and CLK='1') then    --transfer the input
                                         --data to output port at each
                                         --clock cycle
        OUTDATA <= DATA;
      end if;
  end process;
end OSC_ARCH;
 

Q: How do I feed signals to the inputs of my design ?
A:
1.For now, we'll use an on-board DIP switch to feed the inputs. The switch is located right between the two chips. Consult the manual "Hardware and Peripherals User Guide", page 1-9 Table 1-2 to see which switch is connected to which pad position. Then you map that pad position to your specified design input bit through .cst file.
2.For example, if you want bit a(0) in problem 3 to be controlled by the first switch, then put this line in cst file (assume using XC4003):

place instance a<0>_pad: p19;

Q: Is there any thing I need to pay attention to ?
A:
I would like to stress out several issues:

1.The entity name should be always in lower case, if you want to run "make_everything" (although it does not matter in design_analyzer and vhdldbx).
2.Always use "behavioral" (does not matter if it is in lower case or not) after the "architecture" statement. (It does not matter in design_analyzer and vhdldbx, too).
3.Since we are using the DIP switch, try to remove any unnecessary statements like "if" in your code. If you run "make_everything" and got an error that "no xnf file is generated...", then go back to your design and remove some redundant constructs. And try again! In my case, even I used one more "if" statement than it is necessary in my comparator, it does not work...

Q: I ran the "make_everything" successfully. I got the LCA file. But I got error message like "INIT can not be pulled low, DONE can not be pulled high. The LCA file may not be configured properly..." when I ran xcheck...
A:
The problem is from the fact that you did not configure the DIP switches for the xchecker/download cable. The DIP switches(J2 for XC4003 and J1 for XC3020) are located right next to the corresponding download cable. You should configure them according to table 1-9 on page 1-23 in "Hardware and Peripherals User Guide". "X" in the table means don't care. Actually, it is a good idea to check the switch positions before you try to download anything to the FPGA board, cause someone else might have changed them.

About 1st Assignment

Q: I try to debug the VHDL code in problem 1, but I keep getting "ieee_std_logic_1164.ALL not found" error. What could be wrong?
A:
Problem 1 in the first assignment has a lot of syntax errors. You need to find them out. This is to get you familiar with the VHDL syntax. The library is there, but the syntax is wrong. So SYNOPSYS can't find it.

About 2nd Assignment

Q: Where can I get the needed information to finish this assignment ?
A:
You need to look up :

1."Hardware & Peripherals User Guide"
2."Using SYNOPSYS/XILINX for the CES department at CWRU". It is in:
Click here
3.Questions/Answers throughout this FAQ.

Q: What exactly do I need to do for assignment 2 ?
A:

1.You need to know how to write a VHDL, and compile it successfully with SYNOPSYS (refer back to assignment 1).
2.Then you should know how to download the code to the FPGA board. (Refer to the questions about using "make_everything" in this FAQ.) Make sure you have the power on to the board when you download. And also make sure if you connect the power cable to the right place. (You should use J1/J2, depends on which chip, 4003 or 3000, you want to use. Consult the manual I mentioned somewhere in the "XILINX" section in this FAQ.)
3.All the DIP switch positions should be kept the way they are. (They are pre-set).
4.The real download process occurs when you run the XChecker. The command is : xchecker filename.bit So you need to look for the file with .bit extension after you run "make_everything".
5.For now, you just practice till this point. I'll reveal more on how to assign design I/O to particular PINs on the FPGA board. So you can probe and set the I/O for your design. This can be done with the CST file. If you look at the hello.cst file, you'll know the syntax. PXX is the PIN number you want your particular design I/O goes to. DISPLAY can be changed to other I/O name. You need to append "_pad" after the name.
6.I'll come back for more on how to observe the signal outputs with an HP Logic Analyzer. Also, don't worry about how to feed the input signals in at this point. I'll post more when the TAs decide the test/demo details.

Q: The number of available DIP switches are too less for my design ...
A:
Prepare for any change on the assignment. We might announce to scale down the input bits to fit all into 8 bits. For example, in problem 2, we have 4x8+2=34 input bits, but we only got 8 bits available here. If we change all of the 4 inputs (a, b, c, d) from 8 bits to 1 bit, we can make it with only 8 DIP switches.
So, watch for the announcement. But for now, you just practice it such that you can quickly change the code in a second!!

About 3rd Assignment

Q: What is the "BUFGS" error and where is the help ?
A:
Check out the shelf outside the professor's office in Olin, 5th floor. Copies of the slides in the BUFGS presentation in the class will be put there. If you need more copies, contact the professor or David.

Q: How can I write a synthesizable VHDL code ?
A:
Check out the document "hdl_dg.pdf". It is in PDF format, so you need to run "acroread" to read it. Acroread is with other Synopsys programs when you source the startup file for Synopsys. The directory is:

/nfs/papa/xilinx/hdl_dg.pdf

About 4th Assignment

Q: Is the password single digit or multiple digits ?
A:
Use a 1 digit Hex number for password. Use the switches unless we connect a telephone type keypad (there is one in the lab). For a multiple-digit password, you need more effort--you need a seperate FSM to recognize the password.

Misc. Problems

Q: I can't send an e-mail when I click "mail to..." on these pages.
A:
This is because you did not set the Netscape environment properly. Go to "Options". Then choose "Mail and News Preferences". Click on tab "Identity", put your full e-mail address there. Click tab "Servers", and put your server name (for example, alpha.ces.cwru.edu) in STMP Serve line. Leave everything else as default.

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