Problem 2:

    Loop:  LD     F0, 0(R1)
           LD     F6, -8(R1)
           MULTD  F0, F0, F2                 ; >1 from LD F0
           MULTD  F6, F6, F2                 ; >1 from LD F6
           LD     F4, 0(R2)
           LD     F8, -8(R2)
           ADDD   F0, F0, F4                 ; >3 from MULTD F0
           ADDD   F6, F6, F8                 ; >3 from MULTD F6
           SUBI   R1, R1, 16
           SUBI   R2, R2, 16
           SD     8(R2), F0                  ; >2 from ADDD F0
           BNEQZ  R1, Loop
           SD     0(R2), F6                  ; >2 from ADDD F6
                                             ; fills branch delay