High Level Synthesis for Low Power

Shuyu Lei

Low power consumption is a very attractive issue in the current IC industry and research. Due to the emergence of portable application, wireless interface, reliability problem and high cost packaging and cooling requirement, there has been a constantly increasing demand for circuits with low power consumption. The low-level improvement, such as optimization on the layout of standard cell, can not result in trememdous reduction on the power consumtion. Therefore, there are more and more researches on high-level synthesis for the low power problem. The idea is that a better archetecture of the circuit will be more effecient for power saving.

There are three different terms consisting of the equation of the power consumtion, gate output parasitic capacitance, power supply voltage, and state swtching activity frquency. The reduction on either term will cause the reduction on the overall power consumption. In this presentation, we only concentrate on the third term, state switching activity frquency.

Two methods will be proposed in this presentation, one for data dominant circuits, such as DSP; one for Finite State Machine (FSM).

For data dominat circuits, we would like to use the method of power-conscious loop fodling. The key point behind this method is that we can take advantage of the correlation between data, then reduce the the switching activity at the inputs of the multiplier, which dominates the power consumption in most DSP circuits. If we can save the power for multiplication, the overall power consumption on the whole chip will be reduced.

For FSM, we concentrate on the state assignment of the system, because the effecient way to assign the states will cause less switching activities at the inputs of combinations circuits, which consume most power in FSM. To obtain the optimal the state assignment, we exploit the concept of signal probability. We treat the input signals as Stochastic process. then calculate the the probability of the state transitions. And we use this probability to make up of the objective function. Therefore, we can use simulated annealing to get the optimal result.

"Power-conscious High Level Synthesis Using Loop Folding," D. Kim, K. Choi, 34th Design Automation Conference, pp. 441-445.

"Circuit Activity Based Logic Synthesis for Low Power Reliable Operations," K.R. Roy, S.C. Prasad, IEEE Transactions on VLSI Systems, Vol. 14, No. 4, Dec. 1993, pp. 503-513.

"Behavioral Synthesis for Low Power," A. Raghunathan, N.K. Jha, IEEE ICCD, 1994, pp. 318-322.

"A Power Modeling and Characterization Method for Macrocells Using Structure Information," J.Y. Lin, W.Z. Shen, J.Y. Jou, IEEE 1997, pp. 502-506.

"Design of Portable Systems," A.P. Chandrakasan, R. Allmon, A. Stratakos, R.W. Brodersen, IEEE 1994 Custom Intergrated Circuits Conference, pp. 259-266.

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Joan Carletta, carletta@ces.cwru.edu