ECMP 486: Research in VLSI Systems
I am completely open to suggestions as to the
subjects of the final projects; any aspect
of VLSI design automation that we haven't
already covered extensively in class
is fair game. Here are some of my suggestions,
just to help you get started. I will add more
topics as I think of them. Feel free to suggest
your own, or to come in and talk to me.
- Hardware / Software Codesign.
When designing a system, you can decide to buy a
general microprocessor and write software for it
(the cheap but slow-running option), design special
purpose hardware for it (the expensive but fast-
running option), or do something in between, placing
time-critical parts in special purpose hardware
and not-so-critical parts in software. Hardware
/ software codesign determines where to make the
split between hardware and software parts,
and how to deal with the interface.
- Segmented Channel Routing.
Routing for FPGAs is substantially different from
the channel routing for standard cell ASICs that we
studied in class. The primary difference is that
for standard cells, you have complete control over
where the wire segments should go, while for FPGAs,
you must work with existing wire segments.
This problem is called segmented channel routing.
- State Machine Synthesis for Low Power.
One way to reduce the power consumed by a state
machine is to pay special attention to the state
encoding. This is a new area; in the past, the
biggest concerns have been synthesis to reduce
area or critical delay (also fine topics for
a final project).
- Technology Mapping for Non-LUT Based FPGAs.
We studied methods for technology mapping for
XILINX-style (look-up table based) FPGAs in class,
but many other kinds of FPGAs exist, with different
criteria for technology mapping. One popular kind
is mux-based (like those made by Actel).
- High Level Power Estimation.
Given a behavioral description of a circuit,
how can you estimate how much power it will
use once designed and implemented?
- Tools for Automatic Test Pattern Generation.
Automatic test pattern generation (ATPG) analyzes
a circuit to come up with test patterns tailor-made
to test that circuit. This is an extremely expensive
and time-consuming process, and various approaches
(genetic algorithms, for example), have been used
to help speed things up.
- Methods for Partial Scan Flip-Flop Selection.
Full scan, which chains all the flip-flops
in a sequential circuit together into a scan
chain, is used to turn a sequential ATPG problem into
a combinational ATPG problem. However,it requires a
high hardware overhead. Partial scan is
a compromise; put just enough flip-flops in the scan chain
to make test pattern generation easier. A variety of
methods have been proposed for deciding which flip-flops
should be put in the scan chain.