Summary of commands and their effects

source /local/eda/synopsys_setup.csh
Adds the appropriate Synopsys paths and shell variables to your current environment. 

Synopsys Design Analyzer Command Shell. This is the non-graphical version of the Synopsys Design Analyzer. It is useful for running script files (.dcsh) from the command line or from a Makefile. Stores designs in .db format but can export to a variety of file types including EDIF (.sedif) and a Xilinx netlist format (.sxnf) for xmake
Synopsys Design Analyzer. Graphical tool which allows access to VHDL compiler (Design Compiler), mapping and optimization tools for Xilinx (FPGA Compiler for XC4000), and speed and area information. Automatically generates a hierarchical or flattened schematic of the mapped design. All menu options are equivalent to a shell command that can be seen by viewing the command.log and used in your own dc_shell scripts. 
Synopsys Online Documentation.

Xilinx Design Manager: provides easy access to a variety of programs and allows you to choose among cryptic command-line options with a mouse. Programs include XDE/Editlca for viewing the placed and routed FPGA internals, XMAKE for automating translation of Synopsys output or wirelists into FPGA programming files, and XSIMMAKE for extracting the timing information from XMAKE's output for simulation. 
A graphical tool which allows you to examine the layout of the FPGA. The array of CLBs is shown surrounded by the IOBs and pads, connected by the programmable switch networks. To view the functions and flip-flop connections inside a CLB or IOB, select Blk->EditBlk and click on the block. To return to the layout, select Blk->EndBlk. 
Xilinx XMAKE utility: Automatically executes the proper sequence of Xilinx command-line tools for translation of FPGA designs depending on the part type. For XC3000 FPGAs, it runs syn2xnf, xnfmerge, xnfprep, xnfmap, map2lca, apr, and makebits. For XC4000 FPGAs, it runs ppr instead of apr, and for Viewlogic designs it runs wir2xnf instead of syn2xnf. These tools and their options tend to vary from version to version, so XMAKE hides many of these details from the user. 
Xilinx XSIMMAKE utility: Performs one of several simulation preparation flows. The Viewlogic_Fpga_Func flow duplicates a Viewlogic schematic hierarchy and produces a functional .vsm simulation file only. The Viewlogic_Fpga_Timing flow uses the output of the XMAKE process (.lca file) and produces a .vsm file with post-routing delays for simulation with ViewSim. It runs xdelay, lca2xnf, xnfba, xnf2wir, then vsm
Part of Xilinx/Synopsys Interface package: converts a Synopsys .sxnf or .sedif file to Xilinx .xnf format. 
Converts Viewlogic wirelists (e.g. wir/design.1) into Xilinx .xnf format for each component in the design hierarchy. 
Combines all the .xnf files for a design hierarchy into one flattened .xff file. 
Takes a flattened XNF file (.xff), checks for design rule violations and warnings such as very high fanout, gated clocks, and combinational feedthroughs, trims unnecessary logic and writes an .xtf file, and produces a human-readable .prp summary file. 
Translates an .xtf file into a .map file, mapping logic to the actual FPGA logic blocks. 
Automatic Place and Route program for XC3000 parts. Uses a .map file as input and an optional .cst constraint file to specify pad locations. Produces an .lca file that can be viewed with XDM->XDE->Editlca
Partition, Place, and Route program for XC4000 parts. Uses a .map file and an optional .cst constraint file, produces an .lca file. 
Produces .bit file for downloading to an FPGA from .lca file. Optionally produces a .rbt rawbits file which has one bit per character and hence is bigger but simpler to read. 
Traces paths in the LCA layout and writes timing information into the .lca file. 
Translates an input .lca design file into an .xnf file with delays. 
Back-Annotates the output of lca2xnf with labels from the .xff file, since the apr/ppr process cause some names to be lost. Produces a single xnfba.xnf file. 
Converts an .xnf file into a Viewlogic wirelist for use by vsm and ViewSim.

Original work by Scott E. Harrington, Duke Electrical Engineering