Xilinx FPGA DEMO Board XC4003 and XC3020 Frequently Asked Questions


About Using XILINX...

Q: How do I use the "hello.make" script ?
StepsHere are the step to run the demo

(0) If your default shell is not cshell then type: /bin/csh

(1) source /local/eda/synopsys_setup.csh

(2) cd ~/XILINX

(3) ls -l

    There should be two hello files in the XILINX directory.
    hello.make        - This is the source script file to synthesize your design
    hello.vhd         - This is the source file for the xilinx demo board
    hello.cst         - This file maps the vhdl ports to xilinx pins

(4) more hello.make

    This shows how to call make_xilinx_fpga so in future assignments
    you can write your own make file.

    chmod +x filename

    this will make a file read, write, and executable

(4) ./hello.make

    The "./" executes the program from your local directory
    This does the whole synthesis process and creates a hello.bit file
    the hello.bit file contains the bit file for the Xilinx fpga CLB configuration

(5) xchecker hello.bit
    (a) Make source the serial cable is connected to the Workstation and Board
    (b) Make sure the power is connected to the board and is turned on.
    (c) Run xchecker: This downloads the hello.bit file to the Xilinx chip.

(6) The web site contains the hardware manual for the board.

(7) The LEDs should say.....

Q: Where can I find the documentation about downloading my design to the FPGA demonstration board ?


Chapter 1: page 6 Board schematic So you know where the power cable goes to the board. pages 27-29 FPGA Demonstration Board Operation Forget about the PROM thing for now.

Chapter 3: pages 8-9 What you should do before using XChecker. ...

Remember, you must create your own debouce circuit in vhdl when using switches!

Q: What is this "OSC4" thing ?
"OSC4" is an on-chip, internal 5-frequency clock-signal generator. For now, it is available ONLY for XC4000 series FPGAs. It provides internal clock signals in applications where timing is not critical. The available frequencies are determined by FPGA device components, so they are process dependent. Therefore, the available frequencies vary from devices to devices. Nominal frequensies are 8Mhz, 500Khz, 16Khz, 490Hz, and 15Hz. Although there are 5 outputs, only three can be used at a time, with 8 Mhz on one output and one frequency each on any two of the remaining 4 outputs. An error occurs if more than 3 outputs are used at the same time. The internal circuit must be connected through buffers to OSC4 outputs. (From XILINX Development System--Libraries Guide, p 3-388. This guide can be found on the XILINX FTP site mentioned above.)

Q: How do I use this OSC4 in my VHDL design ?
Here is an example:

library ieee;
use ieee.std_logic_1164.all;

entity OSC4TEST is
  port (
         DATA: in std_logic;
         OUTDATA: inout std_logic

architecture OSC4_ARCH of OSC4TEST is
                    --declaire a component defined elsewhere--
  component OSC4    --this example only uses the 500Khz output--
    port (
           F500K: out std_logic   
           --for 8 MHZ, this is F8M, for 15Hz, it is F15--
  end component;

  signal CLK: std_logic;  --an intermediate "node"--

    --this is the VHDL syntax to connect one "node" to another--
    U1: OSC4 port map (F500K => CLK);

    process (CLK)
      if (CLK'event and CLK='1') then    --transfer the input
                                         --data to output port at each
                                         --clock cycle
        OUTDATA <= DATA;
      end if;
  end process;

Q: How do I feed signals to the inputs of my design ?
1.For now, we'll use an on-board DIP switch to feed the inputs. The switch is located right between the two chips.
Consult the manual "Hardware and Peripherals User Guide", page 1-9 Table 1-2 to see which switch is connected to which pad position.
Then you map that pad position to your specified design input bit through .cst file.
2.For example, if you want bit a(0) in problem 3 to be controlled by the first switch, then put this line in .cst file (assume using XC4003):

place instance a<0>_pad: p19;

3.So, if you want "equal" bit to be connected to sw3, the syntax would be place instance equal_pad: p23;
4.If you look up the table, pin 19 is connected to sw1. Also, don't forget to connect your primary outputs (which you want to observe, such as the equal, greater than,...bits in problem 3) to some pins that you know where to probe later on...
5.Use the HP logic analyzer to see the outputs while you can change the input patterns by changing the switches.

Q: Is there any thing I need to pay attention to ?
I would like to stress out several issues:

1.The entity name should be always in lower case, if you want to run "make_xilinx_fpga" (although it does not matter in design_analyzer and vhdldbx).
2.Always use "behavioral" (does not matter if it is in lower case or not) after the "architecture" statement. (It does not matter in design_analyzer and vhdldbx, too).
3.Since we are using the DIP switch, try to remove any unnecessary statements like "if" in your code. If you run "make_everything" and got an error that "no xnf file is generated...", then go back to your design and remove some redundant constructs. And try again! In my case, even I used one more "if" statement than it is necessary in my comparator, it does not work...
Q: I ran the "make_xilinx_fpga" successfully. I got the LCA file. But I got error message like "INIT can not be pulled low, DONE can not be pulled high. The LCA file may not be configured properly..." when I ran xcheck...
The problem is from the fact that you did not configure the DIP switches for the xchecker/download cable. The DIP switches(J2 for XC4003 and J1 for XC3020) are located right next to the corresponding download cable. You should configure them according to table 1-9 on page 1-23 in "Hardware and Peripherals User Guide". "X" in the table means don't care. Actually, it is a good idea to check the switch positions before you try to download anything to the FPGA board, cause someone else might have changed them. 
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