Pins of the XC4000E on the Xilinx Demo Board

The following table lists the pins numbers and names for the 84 pin XC4000 FPGA. The pins are connected to headers surrounding the socket on the demoboard. The numbers on the demoboard headers increase from the inside row to the outside, counter-clockwise. The corners at each header give the starting numbers. For a description of the FPGA Demoboard see the EE FPGA page.

After configuration, any input pin that is not used will be configured as an input with a 50-100 kOhm pull-up resistor. Regular input pins will also be connected to a pull-up resistor of the same value. This is done in the IOB block on the FPGA device.

The pin numbering of the 84 pin FPGA is given in the following figure.

	SPECS Device : XC4003E No. of Logic Gates: 3,000 No. CLB: 100 fsystem freq.: 66 MHz Delay: CLB (1.5-4.7ns, depending on the Speed grade); IOB input 2-4.8ns; IOB output (4.8-12ns). See the Xilinx data book 2000 for more information. XC4005XL: 5,000 logic gates; 196 logic blocks and 66MHz system clock Outputs can sink 12mA for the XC4000E and 3mA for the XC4000XL devices

NOTES:

1. PGCK 1-4: are primary global inputs wich drive each a dedicated internal global net with short delays and minimal skew. If not used, each of these pins can be a user-programmable I/O. On the demobaord PGCK1 (pin 13) can be used for an external oscillator clock input.

2. SGCK1-4: These are four secondary global inputs. . If not used, each of these pins can be a user-programmable I/O.

Reference:

The Programmable Logic Data Book, Xilinx, San Jose, 1997.