EECS 316: FPGA LAB Deadline 11 April 2005


In this Lab you will model a finite state machine (FSM) in VHDL, encode the FSM states and implement it as a sequential circuit using Synopsys. You will then simulate the circuit to verify its behavior. Finally, you will download the circuit code onto the FPGA board, and validate the hardware circuit using the I/O switches and display LEDs.

Problem Statement

The example FSM controls a FIFO Queue but to be practical, consider that we want to design a simple digital controller which monitors cars entering and leaving a parking lot. The operation specs are as follows.

Design Process