ECMP 316: FPGA LAB 2 Deadline 20 April 2005


In this Lab you will design a digital circuit to control the alarm system of a typical residence. You will model the circuit in VHDL, simulate and verify its behavior and then download the circuit code onto the FPGA board, and validate it.


The alarm circuit secures a number of entry/exit points which are connected to the controller. For simplicity, let's assume one entry/exit door connected. The alarm is set from the front panel by entering a "passwd" number. The door must be closed for the alarm to be set. After setting, there is a 30 sec time interval during which one can exit through the door without having the alarm go off. On entering the door, there is also a 30 sec time to reset the alarm safely by keying in the correct "passwd". If the "passwd" is incorrect, there is a second chance to do it within the 30sec. Of course, if no "passwd" is entered the alarm will go off in 30sec.

Inputs: Sensor door input. Keypad input.
Outputs: Alarm output. Led indicators of status.

Note that there may be more than one correct passwds. Assume there are four correct passwds.

Design Process