EECS 317

Assignment 4

Please note the following problems from your text book were done earlier without using simulations. For the following problems from your textbook, please simulate the VHDL code of each problem using the CAD facilities in the Lab. You should also verify and test bench that your code is correct. You should submit a professionally written Lab report describing your results and documentation in detail.

1) Problem 10, page 79
2) Problem 11, page 79
3) Problem 14, page 79

This Assignment is due on April 6.