Frequently Asked Questions

About Using UNIX

Q: I got "/u/../.xinitrc not found" when I startx.
A:
You need to put a file called .xinitrc in your home directory.

Q: I have .xinitrc file in my home directory, but I still got "/u/../.xinitrc:x11emacs not found" error when I startx.
A:
If you copy the file .xinitrc from the place described in CWRU UNIX Cookbook, then most likely you'll have this kind of problem. The solution is to edit your .xinitrc file and remove x11emacs.

Q: I got "can't open display" error when I try to open a window on a remote machine.
A:
You forgot to set xhost and environment. The procedure is like this:

1. Suppose you currently login to papaya in UNIX lab.
2. Suppose you have two windows opened, A and B.
3. In window A, you remote login to, say, earth.
4. Go to window B, and type xhost + (A blank in between).
5. Then come back to window A, and type setenv DISPLAY papaya:0.0.

Q: The computer seems to hang there, or I got "... not responding..".
A:
The network is always the problem, be patient!

About VHDL

Q: I got "component not found" error when I debug my structural VHDL code with "COMPONENT" and "PORT MAP" statements.
A:
Two problems could happen:
1.Check if you put all those component files along with your "main" VHDL that uses them.
2.Check if you put all of them within the "main" VHDL file.
The bottomline is that you can only use one "architecture--begin--end" constrcut in any VHDL file. The way to do this is:

1.  Suppose you have a counter VHDL called counter.vhd
2.  Suppose you have pre-constructed several components like XOR.vhd , AND.vhd , or NOT.vhd
3.  Suppose you want to "interconnect" them by using "PORT   MAP" statement in this counter.vhd
4.  The counter.vhd would look like:

component XOR
  PORT()
component AND
  PORT()
component NOT
  PORT()
  ...mumble, mumble...

--See, this is pretty much similar to a C/C++ program (nevertheless,
--VHDL is still a PROGRAM created by computer people with the same 
--thinking). You need to list the "functions" you pre-defined
--elsewhere with, of course, the argument lists... 

--now come the architecture thing

architecture
  PORT MAP(..mumble, mumble...)
end
   

Q: What does a sensitivity list do in VHDL ?
A:
Remember in VHDL, a process is a way to execute sequential statements. So you need some kind of stimulus outside the "process" to get it executed. These stimulus should be included in the sensitivity list. But there are exceptions. If the process includes one or more "wait" statements (clock), then the sensitivity list is optional.
So the guidline is :

A good practice is to put all primary inputs, including clock and reset, on the sensitivity list. It does not affect the final synthesis process. So no harm to the final circuit if you do so. You might want to do so when you see some error/warning messages like " this process will never execute a wait statement (no other processes will have a chance to run)". And you know your design is a combinational circuit, it does not need a clock.

About Setting Up and using SYNOPSYS

Q: I got "/u/../.. permission denied" error.
A:
Usually this kind of error comes from the conflict among different environmental settings. The best way to resolve this is:

1.  Forget about set up the path in your .tcshrc file. Create a working directory for yourself, say, "synopsys".
2.  Within the directory, create another sub-directory called "WORK". The name WORK is important here.
     SYNOPSYS will store all synthesized, compiled VHDL codes here. But it is not necessary to put your
     source VHDL codes in there. You always have the choice to specify the directory.
3.  Create a file called "start_synop", or whatever you want to call it. Here, I just stick with this name.
4.  Create another file ".synopsys_dc.setup". This name is important.
5.  Put these two files in "synopsys", but not in "WORK".
6.  Every time you want to run SYNOPSYS, type source start_synop within "synopsys".
7.  Then type dc_shell for command-line mode, design_analyzer &   for graphical compiler,
     vhdldbx &   for graphical VHDL simulator and debugger.
8.  To get online manual for SYNOPSYS, just type synop_iview &.

Q: How do I compile and simulate the VHDL code ?
A:
OK. Suppose you have a piece of VHDL code called test1.vhd (it is a 3-bit counter that counts from 0 to 7 and starts over from 0):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

--Define the I/O port--

ENTITY test1 IS
   PORT(
         clk     : IN BIT;
         reset   : IN BIT;
         count   : OUT INTEGER range 0 to 7
       );
END test1;

--define the body (behavior of the circuit)--

ARCHITECTURE my_arch OF test1 IS

--temperary "variable" to hold the value between clocks--
--this is pretty much like the temp variables you would--
--use in a C/C++ program                               --

  signal count_tmp : integer range 0 to 7;
begin
  process
  begin
    wait until (clk'event and clk='1');      --clocking--
    if reset = '1' or count_tmp = 7 then  --reset or start over--
      count_tmp <= 0;
    else
      count_tmp <= count_tmp + 1;        --increment the count--
    end if;
  end process;
  count <= count_tmp;                    --final output--
END my_arch;
     

In the directory with all other VHDL files, type in (%> is your shell prompt):

%>design_analyzer &
      

%>vhdldbx &
      

1.   Add a variable into the trace list by highlighting the variable, say, clk by left click-and-drag
     the mouse with cursor on that variable.
2.   Click the "trace" button in the lower window.
3.   A trace window will show up. For the first selected variable, it takes some time.
4.   Repeat these steps for all other variables you want to trace in the later simulation.
5.   This is a counter example. We first set clk to 0 by clicking on "Stimulus" on the tool bar, upper window,
      then selecting "Assign".
6.   In the assign window, highlight '0' and click OK. Note that "assign ('0') clk" shows in the lower window.
7.    Repeat this for other variables in the trace list (i.e. the variables in the left part of the trace window).
8.    Type in the simulation period you want to perform in the "RUN" box in the lower window. Then click on
      "RUN". See the change in the trace window. Note that SYNOPSYS assigns integers instead of binaries
      for the "count" output here. This is because we use "integer" as the type for that variable. If we further
      decode the output into 3 bits, then that's another story... Every variable will be in binaries.
9.    You can print out the trace diagram through a lab printer, if any.

Q: OK. This is great. But I was clocking "clk" like crazy. Is there any easier way to do it ?
A:
You can write a test bench file to do all this, as well as other routine work, and put all your test schemes in a file. Check out the book "A VHDL Primer" listed in REFERENCE, chapter 11. Or you can go to the following web site and see the format of a testbench file (Seg7TestBench.vhdl):

http://lenkkari.cs.tut.fi/~tuominen/FPGA/FPGA_Demo.html

Blibrary ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behav of testbench is
  signal clk, reset: bit :='0';
  signal count : integer :=0;

component test1
|  port(
        clk     : in bit;
        reset   : in bit;
        count   : out integer range 0 to 7
      );
end component;

begin
  test1A:test1
      port map(clk, reset, count);
  reset <= '1', '0' after 30 ns;
  clk <= not clk after 20 ns;
end behav;

configuration TBCfg of testbench is
   for Behav
      for test1A:test1
         use entity work.test1(MY_ARCH);
      end for;
   end for;
end TBCfg;
   

1.  Do VHDL analyze for the original VHDL (test1.vhd).
2.  Do VHDL analyze for this testbench VHDL (test1_TB.vhd). For this case, you'll see "Error....synthesis...".
    This has something to do with the final logic
    synthesis process. Since this is not the VHDL we'll use for synthesis, it's OK. Just ignore it.
3.  In VHDLDBX, call in the testbench file instead of | original VHDL. Double check it in the upper window.
    The file we need is "TBCFG" for this example.
4.  In this case, we already set the initial values for the variables in the test bench. So we don't have to
    "assign" values again. But we DO need to include the variables in the trace list as explained above.
5.  Set the running time to, say, 100. Click on "RUN"; you should be able to see the change. The beauty is
    that you don't need to assign clk any more. You just keep clicking on "RUN".
6.  You can also "overwrite" the variable values between RUNs. Just use the steps explained above.
7.  This testbench shows a simulation scheme of reseting at time 0, and un-reset after 30 ns.
    The clock period is 20 ns. The initial value for "count" is 0.

Q: How do I assign values to a BIT_VECTOR in VHDLDBX ?
A:
Try this! Suppose you want to assign value 1101 to A which is a BIT_VECTOR (0 TO 3) :

1. Still need to do all the analyze, VHDLDBX, add trace list stuff explained in the previous question.
2. In the bottom line box in the lower window (in VHDLDBX), type in assign "1101" A
3.  Note that the test sequence matters here (from left to right or vice versa), depending on your using
    (3 DOWNTO 0) or (0 TO 3).
4.  Everything else should be pretty much the same as in the previous question.
5.  Finally, note that SYNOPSYS uses HEX numbers to display the value in a bit vector. But you can click on
    the small arrow head to the left of the variable in the trace window to EXPAND the bit vector into individual
    bits. Each bit now has its own trace shown in binary number. Check it out!

Q: How do I "synthesize" a VHDL code into a circuit with logic gates ?
A:
Try the following steps

1.  Make sure you don't have any error during the compilation
2.  In the design analyzer window, click on "File" and select "Elaborate...". This will bring up another window.
3.  Fill in "library" and "design"- "library" is the directory of your VHDL code and "design" is the code name.
4.  Click on OK. After some time, you should be able to see a box in the design analyzer window.
5.  Zoom in to the design by double clicking on the box. Repeat this until you can see the gates within.
6.  You can print it out by FILE-->Plot..

Misc. Problems

Q: I can't send an e-mail when I click "mail to..." on these pages.
A:
This is because you did not set the Netscape environment properly. Go to "Options". Then choose "Mail and News Preferences". Click on tab "Identity", put your full e-mail address there. Click tab "Servers", and put your server name (for example, alpha.ces.cwru.edu) in STMP Serve line. Leave everything else as default.

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