The elements that have been described to this point typically require only a few parameter values to specify completely the electrical characteristics of the element. However, the models for the four semiconductor devices that are included in the SPICE program require many parameter values. Moreover, many devices in a circuit often are defined by the same set of device model parameters. For these reasons, a set of device model parameters is defined on a separate .MODEL card and assigned a unique model name. The device element cards in SPICE then reference the model name. This scheme alleviates the need to specify all of the model parameters on each device element card.
Each device element card contains the device name, the nodes to which the device is connected, and the device model name. In addition, other optional parameters may be specified for each device: geometric factors and an initial condition.
The area factor used on the diode, BJT and JFET device card determines the number of equivalent parallel devices of a specified model. The affected parameters are marked with an asterisunder the heading 'area' in the model descriptions below. Several geometric factors associated with the channel and the drain and source diffusions can be specified on the MOSFET device card.
Two different forms of initial conditions may be specified for devices. The first form is included to improve the dc convergence for circuits that contain more than one stable state. If a device is specified OFF, the dc operating point is determined with the terminal voltages for that device set to zero. After convergence is obtained, the program continues to iterate to obtain the exact value for the terminal voltages. If a circuit has more than one dc stable state, the OFF option can be used to force the solution to correspond to a desired state. If a device is specified OFF when in reality the device is conducting, the program will still obtain the correct solution (assuming the solutions converge) but more iterations will be required since the program must independently converge to two separate solutions. The .NODESET card serves a similar purpose as the OFF option. The .NODESET option is easier to apply and is the preferred means to aid convergence.
The second form of initial conditions are specified for use with the transient analysis. These are true 'initial conditions' as opposed to the convergence aids above. See the description of the .IC card and the .TRAN card for a detailed explanation of initial conditions.
General form: DXXXXXXX N+ N- MNAME <AREA> <OFF> <IC=VD> Examples: DBRIDGE 2 10 DIODE1 DCLMP 3 7 DMOD 3.0 IC=0.2N+ and N- are the positive and negative nodes, respectively. MNAME is the model name, AREA is the area factor, and off indicates an (optional) starting condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification using IC=VD is intended for use with the UIC option on the .TRAN card, when a transient analysis is desired starting from other than the quiescent operating point.
General form: QXXXXXXX NC NB NE <NS> MNAME <AREA> <OFF> <IC=VBE,VCE> Examples: Q23 10 24 13 QMOD IC=0.6,5.0 Q50A 11 26 4 20 MOD1NC, NB, and NE are the collector, base, and emitter nodes, respectively. NS is the (optional) substrate node. If unspecified, ground is used. MNAME is the model name, AREA is the area factor, and OFF indicates an (optional) initial condition on the device for the dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification using IC=VBE,VCE is intended for use with the UIC option on the .TRAN card, when a transient analysis is desired starting from other than the quiescent operating point. See the .IC card description for a better way to set transient initial conditions.
General form: JXXXXXXX ND NG NS MNAME <AREA> <OFF> <IC=VDS,VGS> Examples: J1 7 2 3 JM1 OFFND, NG, and NS are the drain, gate, and source nodes, respectively. MNAME is the model name, AREA is the area factor, and OFF indicates an (optional) initial condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification, using IC=VDS,VGS is intended for use with the UIC option on the .TRAN card, when a transient analysis is desired starting from other than the quiescent operating point (see the .IC card for a better way to set initial conditions).
General form: MXXXXXXX ND NG NS NB MNAME <L=VAL> <W=VAL> <AD=VAL> <AS=VAL> + <PD=VAL> <PS=VAL> <NRD=VAL> <NRS=VAL> <OFF> <IC=VDS,VGS,VBS> Examples: M1 24 2 0 20 TYPE1 M31 2 17 6 10 MODM L=5U W=2U M31 2 16 6 10 MODM 5U 2U M1 2 9 3 0 MOD1 L=10U W=5U AD=100P AS=100P PD=40U PS=40U M1 2 9 3 0 MOD1 10U 5U 2P 2PND, NG, NS, and NB are the drain, gate, source, and bulk (substrate) nodes, respectively. MNAME is the model name. L and W are the channel length and width, in meters. AD and AS are the areas of the drain and source diffusions, in sq-meters. Note that the suffix U specifies microns (1E-6 m) and P sq-microns (1E-12 sq-m). If any of L, W, AD, or AS are not specified, default values are used. The user may specify the values to be used for these default parameters on the .OPTIONS card. The use of defaults simplifies input deck preparation, as well as the editing required if device geometries are to be changed. PD and PS are the perimeters of the drain and source junctions, in meters. NRD and NRS designate the equivalent number of squares of the drain and source diffusions; these values multiply the sheet resistance RSH specified on the .MODEL card for an accurate representation of the parasitic series drain and source resistance of each transistor. PD and PS default to 0.0 while NRD and NRS to 1.0. OFF indicates an (optional) initial condition on the device for dc analysis. The (optional) initial condition specification using IC=VDS,VGS,VBS is intended for use with the UIC option on the .TRAN card, when a transient analysis is desired starting from other than the quiescent operating point. See the .IC card for a better and more convenient way to specify transient initial conditions.
General form: .MODEL MNAME TYPE(PNAME1=PVAL1 PNAME2=PVAL2 ... ) Examples: .MODEL MOD1 NPN BF=50 IS=1E-13 VBF=50The .MODEL card specifies a set of model parameters that will be used by one or more devices. MNAME is the model name, and type is one of the following seven types:
NPN NPN BJT model PNP PNP BJT model D diode model NJF N-channel JFET model PJF P-channel JFET model NMOS N-channel MOSFET model PMOS P-channel MOSFET modelParameter values are defined by appending the parameter name, as given below for each model type, followed by an equal sign and the parameter value. Model parameters that are not given a value are assigned the default values given below for each model type.
The dc characteristics of the diode are determined by the parameters IS and N. An ohmic resistance, RS, is included. Charge storage effects are modeled by a transit time, TT, and a nonlinear depletion layer capacitance which is determined by the parameters CJO, VJ, and M. The temperature dependence of the saturation current is defined by the parameters EG, the energy and XTI, the saturation current temperature exponent. Reverse breakdown is modeled by an exponential increase in the reverse diode current and is determined by the parameters BV and IBV (both of which are positive numbers).
name parameter units default example area ---- --------- ----- ------- ------- ---- 1 IS saturation current A 1.0E-14 1.0E-14 * 2 RS ohmic resistance Ohm 0 10 * 3 N emission coefficient - 1 1.0 4 TT transit-time sec 0 0.1Ns 5 CJO zero-bias junction capacitance F 0 2PF * 6 VJ junction potential V 1 0.6 7 M grading coefficient - 0.5 0.5 8 EG activation energy eV 1.11 1.11 Si 0.69 Sbd 0.67 Ge 9 XTI saturation-current temp. exp - 3.0 3.0 jn 2.0 Sbd 10 KF flicker noise coefficient - 0 11 AF flicker noise exponent - 1 12 FC coefficient for forward-bias - 0.5 depletion capacitance formula 13 BV reverse breakdown voltage V infinite 40.0 14 IBV current at breakdown voltage A 1.0E-3
The bipolar junction transistor model in SPICE is an adaptation of the integral charge control model of Gummel and Poon. This modified Gummel-Poon model extends the original model to include several effects at high bias levels. The model will automatically simplify to the simpler Ebers-Moll model when certain parameters are not specified. The parameter names used in the modified Gummel-Poon model have been chosen to be more easily understood by the program user, and to reflect better both physical and circuit design thinking.
The dc model is defined by the parameters IS, BF, NF, ISE, IKF, and NE which determine the forward current gain characteristics, IS, BR, NR, ISC, IKR, and NC which determine the reverse current gain characteristics, and VAF and VAR which determine the output conductance for forward and reverse regions. Three ohmic resistances RB, RC, and RE are included, where RB can be high current dependent. Base charge storage is modeled by forward and reverse transit times, TF and TR, the forward transit time TF being bias dependent if desired, and nonlinear depletion layer capacitances which are determined by CJE, VJE, and MJE for the B-E junction , CJC, VJC, and MJC for the B-C junction and CJS, VJS, and MJS for the C-S (Collector-Substrate) junction. The temperature dependence of the saturation current, IS, is determined by the energy-gap, EG, and the saturation current temperature exponent, XTI. Additionally base current temperature dependence is modeled by the beta temperature exponent XTB in the new model.
The BJT parameters used in the modified Gummel-Poon model are listed below. The parameter names used in earlier versions of SPICE2 are still accepted.
Modified Gummel-Poon BJT Parameters. name parameter units default example area ---- --------- ----- ------- ------- ---- 1 IS transport saturation current A 1.0E-16 1.0E-15 * 2 BF ideal maximum forward beta - 100 100 3 NF forward current emission coef. - 1.0 1 4 VAF forward Early voltage V infinite 200 5 IKF corner for forward beta high current roll-off A infinite 0.01 * 6 ISE B-E leakage saturation current A 0 1.0E-13 * 7 NE B-E leakage emission coefficient - 1.5 2 8 BR ideal maximum reverse beta - 1 0.1 9 NR reverse current emission coefficient - 1 1 10 VAR reverse Early voltage V infinite 200 11 IKR corner for reverse beta high current roll-off A infinite 0.01 * 12 ISC B-C leakage saturation current A 0 1.0E-13 * 13 NC B-C leakage emission coefficient - 2 1.5 14 RB zero bias base resistance Ohms 0 100 * 15 IRB current where base resistance falls halfway to its min value A infinite 0.1 * 16 RBM minimum base resistance at high currents Ohms RB 10 * 17 RE emitter resistance Ohms 0 1 * 18 RC collector resistance Ohms 0 10 * 19 CJE B-E zero-bias depletion capacitance F 0 2PF * 20 VJE B-E built-in potential V 0.75 0.6 21 MJE B-E junction exponential factor - 0.33 0.33 22 TF ideal forward transit time sec 0 0.1Ns 23 XTF ndence of TF V infinite 25 ITF high-current parameter for effect on TF A 0 * 26 PTF excess phase at freq=1.0/(TF*2PI) Hz deg 0 27 CJC B-C zero-bias depletion capacitance F 0 2PF * 28 VJC B-C built-in potential V 0.75 0.5 29 MJC B-C junction exponential factor - 0.33 0.5 30 XCJC fraction of B-C depletion capacitance - 1 connected to internal base node 31 TR ideal reverse transit time sec 0 10Ns 32 CJS zero-bias collector-substrate capacitance F 0 2PF * 33 VJS substrate junction built-in potential V 0.75 34 MJS substrate junction exponential factor - 0 0.5 35 XTB forward and reverse beta temperature exponent - 0 36 EG energy gap for temperature effect on IS eV 1.11 37 XTI temperature exponent for effect on IS - 3 38 KF flicker-noise coefficient - 0 39 AF flicker-noise exponent - 1 40 FC coefficient for forward-bias depletion capacitance formula - 0.5
The JFET model is derived from the FET model of Shichman and Hodges. The dc characteristics are defined by the parameters VTO and BETA, which determine the variation of drain current with gate voltage, LAMBDA, which determines the output conductance, and IS, the saturation current of the two gate junctions. Two ohmic resistances, RD and RS, are included. Charge storage is modeled by nonlinear depletion layer capacitances for both gate junctions which vary as the -1/2 power of junction voltage and are defined by the parameters CGS, CGD, and PB.
name parameter units default example area ---- --------- ----- ------- ------- ---- 1 VTO threshold voltage V -2.0 -2.0 2 BETA transconductance parameter A/V**2 1.0E-4 1.0E-3 * 3 LAMBDA channel length modulation parameter 1/V 0 1.0E-4 4 RD drain ohmic resistance Ohm 0 100 * 5 RS source ohmic resistance Ohm 0 100 * 6 CGS zero-bias G-S junction capacitance F 0 5PF * 7 CGD zero-bias G-D junction capacitance F 0 1PF * 8 PB gate junction potential V 1 0.6 9 IS gate junction saturation current A 1.0E-14 1.0E-14 * 10 KF flicker noise coefficient - 0 11 AF flicker noise exponent - 1 12 FC coefficient for forward-bias - 0.5 depletion capacitance formula
SPICE provides three MOSFET device models which differ in the formulation of the I-V characteristic. The variable LEVEL specifies the model to be used:
LEVEL=1 -> Shichman-Hodges LEVEL=2 -> MOS2 (as described in [1]) LEVEL=3 -> MOS3, a semi-empirical model(see [1])The dc characteristics of the MOSFET are defined by the device parameters VTO, KP, LAMBDA, PHI and GAMMA. These parameters are computed by SPICE if process parameters (NSUB, TOX, ...) are given, but user-specified values always override. VTO is positive (negative) for enhancement mode and negative (positive) for depletion mode N-channel (P-channel) devices. Charge storage is modeled by three constant capacitors, CGSO, CGDO, and CGBO which represent overlap capacitances, by the nonlinear thin-oxide capacitance which is distributed among the gate, source, drain, and bulk regions, and by the nonlinear depletion-layer capacitances for both substrate junctions divided into bottom and periphery, which vary as the MJ and MJSW power of junction voltage respectively, and are determined by the parameters CBD, CBS, CJ, CJSW, MJ, MJSW and PB. There are two built-in models of the charge storage effects associated with the thin-oxide. The default is the piecewise linear voltage-dependent capacitance model proposed by Meyer. The second choice is the charge-controlled capacitance model of Ward and Dutton [1]. The XQC model parameter acts as a flag and a coefficient at the same time. As the former it causes the program to use Meyer's model whenever larger than 0.5 or not specified, and the charge-controlled model when between 0 and 0.5. In the latter case its value defines the share of the channel charge associated with the drain terminal in the saturation region. The thin-oxide charge storage effects are treated slightly different for the LEVEL=1 model. These voltage-dependent capacitances are included only if TOX is specified in the input description and they are represented using Meyer's formulation.
There is some overlap among the parameters describing the junctions, e.g. the reverse current can be input either as IS (in A) or as JS (in A/m**2). Whereas the first is an absolute value the second is multiplied by AD and AS to give the reverse current of the drain and source junctions respectively. This methodology has been chosen since there is no sense in relating always junction characteristics with AD and AS entered on the device card; the areas can be defaulted. The same idea applies also to the zero-bias junction capacitances CBD and CBS (in F) on one hand, and CJ (in F/m**2) on the other. The parasitic drain and source series resistance can be expressed as either RD and RS (in ohms) or RSH (in ohms/sq.), the latter being multiplied by the number of squares NRD and NRS input on the device card.
name parameter units default example ---- --------- ----- ------- ------- 1 LEVEL model index - 1 2 VTO zero-bias threshold voltage V 0.0 1.0 3 KP transconductance parameter A/V**2 2.0E-5 3.1E-5 4 GAMMA bulk threshold parameter V**0.5 0.0 0.37 5 PHI surface potential V 0.6 0.65 6 LAMBDA channel-length modulation (MOS1 and MOS2 only) 1/V 0.0 0.02 7 RD drain ohmic resistance Ohm 0.0 1.0 8 RS source ohmic resistance Ohm 0.0 1.0 9 CBD zero-bias B-D junction capacitance. F 0.0 20FF 10 CBS zero-bias B-S junction capacitance. F 0.0 20FF 11 IS bulk junction saturation current A 1.0E-14 1.0E-15 12 PB bulk junction potential V 0.8 0.87 13 CGSO gate-source overlap capacitance per meter channel width F/m 0.0 4.0E-11 14 CGDO gate-drain overlap capacitance per meter channel width F/m 0.0 4.0E-11 15 CGBO gate-bulk overlap capacitance per meter channel length F/m 0.0 2.0E-10 16 RSH drain and source diffusion sheet resisitance W/sq. 0.0 10.0 17 CJ zero-bias bulk junction bottom cap. per sq-meter of junction area F/m**2 0.0 2.0E-4 18 MJ bulk junction bottom grading coef. - 0.5 0.5 19 CJSW zero-bias bulk junction sidewall cap. per meter of junction perimeter F/m 0.0 1.0E-9 20 MJSW bulk junction sidewall grading coef. - 0.33 21 JS bulk junction saturation current per sq-meter of junction area A/m**2 1.0E-8 22 TOX oxide thickness meter 1.0E-7 1.0E-7 23 NSUB substrate doping 1/cm**3 0.0 4.0E15 24 NSS surface state density 1/cm**2 0.0 1.0E10 25 NFS fast surface state density 1/cm**2 0.0 1.0E10 26 TPG type of gate material: - 1.0 +1 opp. to substrate -1 same as substrate 0 Al gate 27 XJ metallurgical junction depth meter 0.0 1U 28 LD lateral diffusion meter 0.0 0.8U 29 UO surface mobility cm**2/V-s 600 700 30 UCRIT critical field for mobility degradation (MOS2 only) V/cm 1.0E4 1.0E4 31 UEXP critical field exponent in mobility degradation (MOS2 only) - 0.0 0.1 32 UTRA transverse field coef (mobility) (deleted for MOS2) - 0.0 0.3 33 VMAX maximum drift velocity of carriers m/s 0.0 5.0E4 34 NEFF total channel charge (fixed and mobile) coefficient (MOS2 only) - 1.0 5.0 35 XQC thin-oxide capacitance model flag and coefficient of channel charge share attributed to drain (0-0.5) - 1.0 0.4 36 KF flicker noise coefficient - 0.0 1.0E-26 37 AF flicker noise exponent - 1.0 1.2 38 FC coefficient for forward-bias depletion capacitance formula - 0.5 39 DELTA width effect on threshold voltage (MOS2 and MOS3) - 0.0 1.0 40 THETA mobility modulation (MOS3 only) 1/V 0.0 0.1 41 ETA static feedback (MOS3 only) - 0.0 1.0 42 KAPPA saturation field factor (MOS3 only) - 0.2 0.5
[1] A. Vladimirescu and S. Liu, "The Simulation of MOS Integrated Circuits Using SPICE2", ERL Memo No. ERL M80/7,Electronics Research Laboratory, University of California, Berkeley, Oct. 1980.