SPICE Models

• The complexity of the behavior of the short-channel MOS transistor has resulted in a variety of models of different accuracy and computing efficiency.

 

• The LEVEL parameter in the model statement selects the model:
• LEVEL 1 :
• Implements the Shichman-Hodges model, which is based on the square law long-channel expressions.
• Best used to verify a manual analysis.

 

• LEVEL 2 :
• Geometry-based model, which uses detailed device physics to define its equations.
• It handles effects such as velocity saturation , mobility degradation and DIBL but is too complex and inaccurate to handle all 3D effects.

SPICE Models

• LEVEL 3 :
• A semi-empirical model (depends on measured device data to define its parameters).

 

• LEVEL 4 :
• Berkeley Short-Channel IGFET Model ( BSIM ).
• Provides an analytically simple model that is based on a small number of parameters extracted from experimental data.
• It is accurate as well as simple and is the most popular model.

 

• LEVEL 5 - n :
• There are many other models supplied by SPICE vendors and semiconductor manufacturers.

 

• Some of the parameters on the following slides are redundant.
• For example, PHI can be computed from process model parameters.
• User-defined values always override those that can be computed.

SPICE Parameters LEVELs 1-3

Parameter Name	Symbol	SPICE name	Units	Default Value
SPICE Model Index		LEVEL	-	1
Zero-Bias Threshold Voltage	VT0	VTO	V	0
Process Transconductance	k'	KP	A/V2	1.0E-5
Body-Bias Parameter	g	GAMMA	V0.5	0
Channel Modulation	l	LAMBDA	1/V	0
Oxide Thickness	tox	TOX	m	1.0E-7
Lateral Diffusion	xd	LD	m	0
Metallurgical Junction Depth	xj	XJ	m	0
Surface Inversion Potential	2|fF|	PHI	V	0.6
Substrate Doping	NA, ND	NSUB	cm-3	0
Surface-State Density	Qss/q	NSS	cm-3	0
Fast Surface-State Density		NFS	cm-3	0
Total Channel Charge Coef		NEFF	-	1
Type of Gate Material		TPG	-	1
Surface Mobility	m0	U0	cm2/V-sec	600
Maximum Drift Velocity	umax	VMAX	m/s	0
Mobility Critical Field	Ecrit	UCRIT	V/cm	1.0E4
Critical Field Exponent in MD		UEXP	-	0

SPICE Parameters LEVELs 1-3

Parameter Name	Symbol	SPICE name	Units	Default Value
Transverse Field Exponent (mobility)		UTRA	-	0
Source Resistance	RS	RS	W	0
Drain Resistance	RD	RD	W	0
Sheet Resistance (Source/Drain)	R/sq	RSH	W/sq	0
Zero-Bias Bulk Junction Cap	Cj0	CJ	F/m2	0
Bulk Junction Grading Coeff.	m	MJ	-	0.5
Zero-Bias Side-Wall Junction Cap.	Cjsw0	CJSW	F/m	0
Side-Wall Grading Coeff.	msw	MJSW	-	0.3
Gate-Bulk Overlap Cap.	CgbO	CGBO	F/m	0
Gate-Source Overlap Cap.	CgsO	CGSO	F/m	0
Gate-Drain Overlap Cap.	CgdO	CGDO	F/m	0
Bulk Junction Leakage Current	IS	IS	A	0
Bulk Junction Leakage Current Density	JS	JS	A/m2	1E-8
Bulk Junction Potential	f0	PB	V	0.8

SPICE Individual Transistor Parameters

• The following parameters are specified on the device line, not within the transistor.

Parameter Name	Symbol	SPICE name	Units	Default Value
Drawn Length	L	L	m	-
Effective Width	W	W	m	-
Source Area	AREA	AS	m2	0
Drain Area	AREA	AD	m2	0
Source Perimeter	PERIM	PS	m	0
Drain Perimeter	PERIM	PD	m	0
Squares of Source Diffusion		NRS	-	1
Squares of Drain Diffusion		NRD	-	1

• Note that zero is assumed for many of these if left unspecified !
• NRS and NRD multiply the sheet resistance RSH specified in the model to give the series source and drain resistance.

Manual-Analysis Model

• Ignoring short-channel effects leads to grossly inaccurate and overly optimistic results.
• However, the simplified model for the velocity-saturated device is too complex for manual analysis.
• Using SPICE simulations as an ad hoc design strategy doesn't permit a conceptual understanding of the basic operation of the circuit.

 

• Several approaches are possible.
• One possibility is to use the long-channel equations:

Manual-Analysis Model

• And then "adjust" the dominant transistor parameters (k' and l ) so that a reasonable approximation of the current is obtained in the regions of interest.

 

• The performance of a MOS device is primarily determined by the maximum available current (V _GS = V _DS = supply voltage).
• Therefore, a good matching in this region is essential.

• The curves shown above are for a short-channel device withV _GS = 5V and an "matching" long-channel device for V _DS at 5V.

Manual-Analysis Model

• The match was obtained by adjusting k' and l of the long-channel device.
• Note that substantial errors result in other regions, e.g., for small values of V _GS or other values of supply voltage.

 

• Note that this model yields pessimistic results (which is desirable).

 

• For example:

• We can now plug these numbers into the long-channel transistor model for the saturated region, yielding a set of simultaneous equations.

Manual-Analysis Model

• Example (cont)

• Setting I _DN , I _DP , V _DS equal to the values/parameters obtained from the simulation and solving yields LEVEL 1 k' and l values.

 

• e.g. the computed k' value is 1.96E-5 while the LEVEL 2 parameter is 8.0E-5 , a factor of 4 larger !