ECMP 486: Research in VLSI Systems
Reading List
Reading will be assigned as the semester progresses, so
that we can tailor the class to the interests of the
participants.
Calendar of Classes
Click on a date to jump to the reading list for that class day.
There is no reading assigned for this class. The
instructor will provide an introduction to the
course, and review course policies.
There is no reading assigned for this class. The
instructor will review introductory material.
B.W. Kernighan and S. Lin,
"An Efficient Heuristic Procedure for Partitioning Graphs,"
The Bell System Technical Journal,
Vol. 49, February 1970, pp. 291 - 307.
C.M. Fiduccia and R.M. Mattheyses,
"A Linear-Time Heuristic for Improving Network Partitions,"
Proceedings of the 19th Design Automation Conference,
June 1982, pp. 241 - 247.
J.P. Cohoon and W.D. Paris,
"Genetic Placement,"
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems,
Vol. CAD-6, No. 6,
November 1987, pp. 956 - 964.
Adrian Thompson,
"Silicon Evolution,"
Proceedings of Genetic Programming 1996,
J.R. Koza et. al. (editors), MIT Press, 1996,
pp. 444 - 452.
S. Kirkpatrick, C.D. Gelatt, Jr., and M.P. Vecchi,
"Optimization by Simulated Annealing,"
Science,
Vol. 220, No. 4598, 13 May 1983, pp. 671 - 680.
Additional reference on Simulated Annealing:
D.S. Johnson, C.R. Aragon, L.A. McGeoch, and C. Schevon,
"Optimization by Simulated Annealing: An Experimental
Evaluation; Part I: Graph Partitioning,"
Operations Research,
Vol. 37, No. 6, November-December 1989, pp. 865 - 892.
C.-W. Yeh, C.-K. Cheng, and T.-T.Y. Lin,
"Optimization by Iterative Improvement: An Experimental
Evaluation on Two-Way Partitioning,"
IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems,
Vol. 14, No. 2, February 1995, pp. 145 - 153.
Additional references on the Primal-Dual algorithm:
C.-W. Yeh, C.-K. Cheng, and T.-T.Y. Lin,
"A General Purpose Multiple Way Partitioning Algorithm,"
Proceedings of the 28th ACM/IEEE Design Automation Conference,
1991, pp. 421 - 426.
Y.-C. Wei and C.-K. Cheng,
"Towards Efficient Hierarchical Designs by Ratio Cut Partitioning,"
Digest of Papers from the 1989 International Conference on
Computer Aided Design (ICCAD),
1989, pp. 298 - 301.
There is no assigned paper for today; we will
clean up any issues that remain in the papers
we've already discussed, and I will give a brief
overview of a few other partitioning and
placement algorithms.
Additional references:
N.R. Quinn, Jr.,
"The Placement Problem as Viewed from the Physics of
Classical Mechanics,"
Proceedings of the Design Automation Conference,
1975, pp. 67 - 72.
C.-K. Cheng and E.S. Kuh,
"Module Placement Based on Resistive Network Optimization,"
IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems,
Vol. CAD-3, No. 3, July 1984, pp. 218 - 225.
D. Deutsch,
"A 'Dogleg' Channel Router,"
Proceedings of the Design Automation Conference,
July 1976, pp. 425 - 433.
C.Y.R. Chen, C.Y. Hou, and U. Singh,
"Optimal Algorithms for Bubble Sort Based
Non-Manhattan Channel Routing,"
IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems,
Vol. 13, No. 5, May 1994, pp. 603 - 609.
Additional references:
K. Chaudhary and P. Robinson,
"Channel Routing by Sorting,"
IEEE Transactions on Computer-Aided Design,
Vol. 10, No. 6, June 1991, pp. 754 - 760.
D. Wang,
Proceedings of the 28th ACM/IEEE Design Automation Conference,
1991.
R.J. Francis,
"A Tutorial on Logic Synthesis for Lookup-Table
Based FPGAs,"
Proceedings of the International Conference
on Computer Design,
1992, pp. 40 - 47.
Additional reference:
N.-S. Woo,
"A Heuristic Method for FPGA Technology Mapping Based
on Edge Visibility,"
Proceedings of the 28th ACM/IEEE Design Automation
Conference,
1991, pp. 248 - 251.
C.-S. Chen, Y.-W. Tsay, T. Hwang, A.C.H. Wu, and Y.-L. Lin,
"Combining Technology Mapping and Placement for Delay-Minimization
in FPGA Designs,"
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems,
Vol. 14, No. 9, September 1995,
pp. 1076 - 1084.
F.J. Kurdahi and C. Ramachandran,
"Evaluating Layout Area Tradeoffs for High Level
Applications,"
IEEE Transactions on Very Large Scale Integration (VLSI)
Systems,
Vol. 1, No. 1, March 1993, pp. 46 - 55.
R.A. Walker and S. Chaudhuri,
"Introduction to the Scheduling Problem,"
IEEE Design and Test of Computers,
Summer 1995, pp. 60 - 69.
There are some
notes on parts of Walker's paper
that came out too dark to read in the photocopies.
S. Devadas and A.R. Newton,
"Algorithms for Hardware Allocation in Data Path Synthesis,"
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems,
Vol. 8, No. 7, July 1989, pp. 768 - 781.
F.N. Najm,
"A Survey of Power Estimation Techniques in VLSI Circuits,"
IEEE Transactions on Very Large Scale Integration (VLSI)
Systems,
Vol. 2, No. 4, December 1994,
pp. 446 - 455.
Nand Kumar, Srinivas Katkoori, Leo Rader, and Ranga Vemuri,
"Profile-Driven Behavioral Synthesis for
Low-Power VLSI Systems",
IEEE Design & Test of Computers, Fall 1995, pp.70-84.
B.T. Murray and J.P. Hayes,
"Testing ICs: Getting to the Core of the Problem,"
IEEE Computer,
November 1996, pp. 32 - 38.
N.A. Touba and B. Pouya,
"Using Partial Isolation Rings to Test Core-Based Designs,"
IEEE Design & Test of Computers,
October-December 1997,
pp. 52 - 59.
F. Corno, P. Prinetto, M. Rebaudengo, and M.S. Reorda,
"GATTO: A Genetic Algorithm for
Automatic Test Pattern Generation
for Large Synchronous Sequential Circuits,"
IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems,
vol. 15, no. 8, August 1996.
M. Potkonjak, S. Dey, and R.K. Roy,
"Behavioral Synthesis of Area-Efficient Testable Designs
Using Interaction Between Hardware Sharing and Partial Scan,"
IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems,
vol. 14, no. 9, September 1995.
N. Mukherjee, M. Kassab, J. Rajski, and J. Tyszer,
"Arithmetic Built-In Self Test for High-Level Synthesis,"
Proceedings of the 13th IEEE VLSI Test Symposium (VTS95),
May 1995,
pp. 132 - 139.
I.D. Dear, C. Dislis, A.P. Ambler, and J. Dick,
"Economic Effects in Design and Test,"
IEEE Design & Test of Computers,
December 1991,
pp. 64 - 77.
Francis Martin will talk about his current research
in the test of embedded systems.
Final project presentation.
Meyyapan Ramanathan will talk about high level
synthesis for digital signal processing applications.
Here is
the abstract for his talk.
Final project presentations.
Tarachand Pagarani will talk about design verification
borrowing techniques from circuit testing.
Here is
the abstract for his talk.
Elie Yarack will talk about design-for-testability
at a high level of design abstraction.
Here is
the abstract for his talk.
Final project presentations.
Ben Floering will talk about over-the-cell routing.
Here is
the abstract for his talk.
Li Tianliang will talk about test of embedded
systems.
Here is
the abstract for his talk.
Final project presentations.
Jake Garver will talk.
Here is the abstract for his talk.
Shuyu Lei will talk.
Here is the abstract for his talk.
Here is a link back to the ECMP 486 Home Page.
Joan Carletta,
carletta@ces.cwru.edu