Reconfigurable Computing Chip EECS 317: Computer Design Laboratory Configurable Logic Bock

Instructor: Prof. Chris Papachristou     Office: 502 Olin, (216)-368-5277, cap2@po.cwru.edu
Instructor: Francis Wolff     Office: 514 Olin, (216)-368-5038, wolff@eecs.cwru.edu
Lab Assistant: T Gorn     Office: 514 Olin, (216)-368-5038, gorn@case.edu
Some of our sponsors: Synopsys, Inc.      Xilinx, Inc.      Altera, Inc.

Course Outline PDF file  
VHDL 1-bit adder pdf file ppt file
VHDL delay models, std_ulogic and with-select-when pdf file ppt file
VHDL Simulator: vhdlan, vhdlsim and the 1-bit adder test bench pdf file    updated ppt file
VHDL N-bit adder: if-generate pdf file ppt file
VHDL Synthesis: dc_shell and design_analyzer pdf file ppt file
VHDL state machines: process, rising_edge and case pdf file ppt file
Lab Project 1: Parking Controller Due April 11 HTML File
Lab Project 2: Alarm Controller Due April 20 HTML File
VHDL standard cell libraries

MSU Standard Cell Library

.pdf file .ppt file
Xilinx demo board demo board faq

board description

demo board manual.pdf file

synthesis commands

xchecker commands

README_xilinx_howto.txt

hello.vhd

hello.cst

hello.make

hello.bit

Previous Information Older information  


Related Links
FAQs Compact VHDL summary

VHDL Quick Reference Guide

VHDL Reference material

Recursion: Implementing Decoders

Examples of VHDL Descriptions

VHDL'87 vs VHDL'93

VHDL FAQs

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VHDL Packages & Models Source Code UART, LSFR, TEXTIO

Standard VHDL Packages

Synthesizable Arithmetic Library

Synthesizable Altera FPGA LPM models

Processors

Other Packages & Models

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VHDL IP cores OpenCores.Org

Memory Cores: FIFO, DualPort Memory

FIFO, DualPort Memory

Scalable SCMOS Standard Cell Library

MSU Standard Cell Library

MSU Standard Cell Library (vhdl timing)

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VHDL Description VHDL 93 BNF grammar

Reserved VHDL words

cached webpage
CAD Tools Quick Synopsys Setup
Academic Research CAD Tools
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Organizations The Hamburg VHDL archive
IP-Based Embedded System Design
VHDL International
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Newsletter VHDL Times no cache
CWRU EECS
VLSI CAD Group
EECS 318 CAD

EECS 322 Computer Architecture using MIPS

Other Computer Engineering Classes

Informative Links

Unix Unix Help Pages cached webpage
Artificial Humans Can a Machine Ever Become Self-aware? cached webpage
Hollywood and Neural Networks Terminator II cached webpage
VHDL Neural Networks Study, Implementation, and Evolution of the Neural Networks not cached