Instructor: Professor Daniel Saab Office: 516 Olin, 216-368-2494,
Instructor: Francis Wolff Office: 514 Olin, (216)-368-5038,
Some of our sponsors: Synopsys, Inc.      Xilinx, Inc.


Lecture 1 System-on-a-Chip (SoC) Introduction Adobe (.pdf) Powerpoint (.ppt)
Lecture 2
and Assignment 1
(Due Tues, Sept 5)
The VHDL Full Adder Adobe (.pdf) Powerpoint (.ppt)
Lecture 3 The VHDL N-bit Adder Adobe (.pdf) Powerpoint (.ppt)
Lecture 4
and Assignment 2
(Due Tues, Sept 19)
Delay models and std_ulogic Adobe (.pdf) Powerpoint (.ppt)
Lecture 5 AOIs, With-Select-When, When-Else Adobe (.pdf) Powerpoint (.ppt)
Lecture 6 State Machines Adobe (.pdf) Powerpoint (.ppt)
Lecture 7 Multicycle MIPS CPU Adobe (.pdf) Powerpoint (.ppt)
Lecture 8
and Assignment 3
(Dues Thurs, Oct 5)
VHDL Processes Adobe (.pdf) Powerpoint (.ppt)
Lecture 9
and Assignment 4
(Dues Tues, Oct 17)
VHDL Synopsys Synthesis: dc_shell Adobe (.pdf) Powerpoint (.ppt)
Lecture 10 Improving Memory Access: Direct and Temporal Caches Adobe (.pdf) Powerpoint (.ppt)
Lecture 11 DSP Architectures: Basic Adobe (.pdf) Powerpoint (.ppt)
Lecture 12 DSP Architectures: Advanced Adobe (.pdf) Powerpoint (.ppt)
Lecture 13 VHDL Synopsys Simulator: vhdlan, vhdlsim, vhdldbx Adobe (.pdf) Powerpoint (.ppt)
Lecture 14
and Assignment 5 and 6
(Dues Thurs, Oct 26)
VHDL Synopsys Simulator: textio, clocks, wait, test benches Adobe (.pdf) Powerpoint (.ppt)

Related Links

CAD Guidelines ASIC DFT Synchronous design techniques
VHDL and Verlog design techniques
Infineon VHDL coding requirements
Gate clocks in asynchronous and synchronous design
The Seven Deadly Sins of Scan-Based Designs
CAD Tools Quick Synopsys Setup
Academic Research CAD Tools
Organizations The Hamburg VHDL archive
IP-Based Embedded System Design
VHDL International
Newsletter VHDL Times --
VHDL Description VHDL 93 BNF grammar cached webpage
EECS 322 Computer Architecture using MIPS Other Computer Engineering Classes

Informative Links

Unix Unix Help Pages cached webpage
Artificial Humans Can a Machine Ever Become Self-aware? cached webpage
Hollywood and Neural Networks Terminator II cached webpage
VHDL Neural Networks Study, Implementation, and Evolution of the Neural Networks not cached

Prerequisites by Topic


Course Website

Topics (until October 17)

The first half of the course will focus on a high-level design, simulation and finally synthesis using a high level design language called VHDL.

There will be an assignment given approximately every week. Of the six assignments, the lowest grade will be dropped.

Professor Saab will teach the course from October 19 until the end of the semester and give his own assignments.

Office hours