0. TABLE OF CONTENTS | 1. INTRODUCTION | 2. CIRCUIT DESCRIPTION |
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3. CIRCUIT ELEMENTS AND MODELS | 4. ANALYSES AND OUTPUT CONTROL | 5. INTERACTIVE INTERPRETER |
6. BIBLIOGRAPHY | APPENDIX A | APPENDIX B |
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[2] | T. Sakurai and A. R. Newton, A Simple MOSFET Model for Circuit Analysis and its application to CMOS gate delay analysis and series-connected MOSFET Structure ERL Memo No. ERL M90/19, Electronics Research Laboratory, University of California, Berkeley, March 1990 |
[3] | B. J. Sheu, D. L. Scharfetter, and P. K. Ko, SPICE2 Implementation of BSIM ERL Memo No. ERL M85/42, Electronics Research Laboratory University of California, Berkeley, May 1985 |
[4] | J. R. Pierret, A MOS Parameter Extraction Program for the BSIM Model ERL Memo Nos. ERL M84/99 and M84/100, Electronics Research Laboratory University of California, Berkeley, November 1984 |
[5] | Min-Chie Jeng, Design and Modeling of Deep- Submicrometer MOSFETSs ERL Memo Nos. ERL M90/90, Electronics Research Laboratory University of California, Berkeley, October 1990 |
[6] | Soyeon Park, Analysis and SPICE implementation of High Temperature Effects on MOSFET, Master's thesis, University of California, Berkeley, December 1986. |
[7] | Clement Szeto, Simulator of Temperature Effects in MOSFETs (STEIM), Master's thesis, University of California, Berkeley, May 1988. |
[8] | J.S. Roychowdhury and D.O. Pederson, Efficient Transient Simulation of Lossy Interconnect, Proc. of the 28th ACM/IEEE Design Automation Conference, June 17-21 1991, San Francisco. Available as html and pdf formats. |
[9] | A. E. Parker and D. J. Skellern, An Improved FET Model for Computer Simulators, IEEE Trans CAD, vol. 9, no. 5, pp. 551-553, May 1990. |
[10] | R. Saleh and A. Yang, Editors, Simulation and Modeling, IEEE Circuits and Devices, vol. 8, no. 3, pp. 7-8 and 49, May 1992 |
[11] | H. Statz, et al., GaAs FET Device and Circuit Simulation in SPICE, IEEE Transactions on Electron Devices, V34, Number 2, February, 1987 pp160-169. |