SPICE 3 User's Manual

SPICE 3 User's Manual - Section 3

0. TABLE OF CONTENTS	1. INTRODUCTION	2. CIRCUIT DESCRIPTION
3. CIRCUIT ELEMENTS AND MODELS	4. ANALYSES AND OUTPUT CONTROL	5. INTERACTIVE INTERPRETER
6. BIBLIOGRAPHY	APPENDIX A	APPENDIX B

3 CIRCUIT ELEMENTS AND MODELS

Data fields that are enclosed in less-than and greater-than signs ('< >') are optional. All indicated punctuation (parentheses, equal signs, etc.) is optional but indicate the presence of any delimiter. Further, future implementations may require the punctuation as stated. A consistent style adhering to the punctuation shown here makes the input easier to understand. With respect to branch voltages and currents, SPICE uniformly uses the associated reference convention (current flows in the direction of voltage drop).

3.1 ELEMENTARY DEVICES

3.1.1 Resistors

General form:

     RXXXXXXX N1 N2 VALUE

Examples:

     R1 1 2 100
     RC1 12 17 1K

N1 and N2 are the two element nodes. VALUE is the resistance (in ohms) and may be positive or negative but not zero.

3.1.2 Semiconductor Resistors

General form:

     RXXXXXXX N1 N2 <VALUE> <MNAME> <L=LENGTH> <W=WIDTH> <TEMP=T>

Examples:

     RLOAD 2 10 10K
     RMOD 3 7 RMODEL L=10u W=1u

This is the more general form of the resistor presented in section 6.1, and allows the modeling of temperature effects and for the calculation of the actual resistance value from strictly geometric information and the specifications of the process. If VALUE is specified, it overrides the geometric information and defines the resistance. If MNAME is specified, then the resistance may be calculated from the process information in the model MNAME and the given LENGTH and WIDTH. If VALUE is not specified, then MNAME and LENGTH must be specified. If WIDTH is not specified, then it is taken from the default width given in the model. The (optional) TEMP value is the temperature at which this device is to operate, and overrides the temperature specification on the .OPTION control line.

3.1.3 Semiconductor Resistor Model (R)

The resistor model consists of process-related device data that allow the resistance to be calculated from geometric information and to be corrected for temperature. The parameters available are:

name parameter units default example
TC1 first order temperature coeff. Z°C^-1 0.0 -
TC2 second order temperature coeff. Z°C^-2 0.0 -
RSH sheet resistance ohm/[] - 50
DEFW default width m 1e-6 2e-6
NARROW narrowing due to side etching m 0.0 1e-7
TNOM parameter measurement temperature °C 27 50

name	parameter	units	default	example
TC1	first order temperature coeff.	Z°C^-1	0.0	-
TC2	second order temperature coeff.	Z°C^-2	0.0	-
RSH	sheet resistance	ohm/[]	-	50
DEFW	default width	m	1e-6	2e-6
NARROW	narrowing due to side etching	m	0.0	1e-7
TNOM	parameter measurement temperature	°C	27	50

The sheet resistance is used with the narrowing parameter and L and W from the resistor device to determine the nominal resistance by the formula

                              L - NARROW
                      R = RSH ----------
                              W - NARROW

DEFW is used to supply a default value for W if one is not specified for the device. If either RSH or L is not specified, then the standard default resistance value of 1k Z is used. TNOM is used to override the circuit-wide value given on the .OPTIONS control line where the parameters of this model have been measured at a different temperature. After the nominal resistance is calculated, it is adjusted for temperature by the formula:

                                                   2
        R(T) = R(T ) [1 + TC1 (T - T ) + TC2 (T-T ) ]
                  0                 0            0

3.1.4 Capacitors

General form:

     CXXXXXXX N+ N- VALUE <IC=INCOND>

Examples:

     CBYP 13 0 1UF
     COSC 17 23 10U IC=3V

N+ and N- are the positive and negative element nodes, respectively. VALUE is the capacitance in Farads.

The (optional) initial condition is the initial (time-zero) value of capacitor voltage (in Volts). Note that the initial conditions (if any) apply 'only' if the UIC option is specified on the .TRAN control line.

3.1.5 Semiconductor Capacitors

General form:

     CXXXXXXX N1 N2 <VALUE> <MNAME> <L=LENGTH> <W=WIDTH> <IC=VAL>

Examples:

     CLOAD 2 10 10P
     CMOD 3 7 CMODEL L=10u W=1u

This is the more general form of the Capacitor presented in section 6.2, and allows for the calculation of the actual capacitance value from strictly geometric information and the specifications of the process. If VALUE is specified, it defines the capacitance. If MNAME is specified, then the capacitance is calculated from the process information in the model MNAME and the given LENGTH and WIDTH. If VALUE is not specified, then MNAME and LENGTH must be specified. If WIDTH is not specified, then it is taken from the default width given in the model. Either VALUE or MNAME, LENGTH, and WIDTH may be specified, but not both sets.

3.1.6 Semiconductor Capacitor Model (C)

The capacitor model contains process information that may be used to compute the capacitance from strictly geometric information.

name parameter units default example
CJ junction bottom capacitance F m^-2 - 5e-5
CJSW junction sidewall capacitance F m^-1 - 2e-11
DEFW default device width m 1e-6 2e-6
NARROW narrowing due to side etching m 0.0 1e-7

name	parameter	units	default	example
CJ	junction bottom capacitance	F m^-2	-	5e-5
CJSW	junction sidewall capacitance	F m^-1	-	2e-11
DEFW	default device width	m	1e-6	2e-6
NARROW	narrowing due to side etching	m	0.0	1e-7

The capacitor has a capacitance computed as

 CAP = CJ (LENGTH - NARROW) (WIDTH - NARROW) + 2 CJSW (LENGTH + WIDTH - 2 NARROW)

3.1.7 Inductors

General form:

     LYYYYYYY +Node -Node VALUE <IC=INCOND>

Examples:

     LLINK  42 69 1UH
     LSHUNT 23 51 10U IC=15.7MA

+Node and -Node are the positive and negative element nodes, respectively. VALUE is the inductance in henries.

The (optional) initial condition is the initial (time-zero) value of inductor current (in amps) that flows from N+, through the inductor, to N-. Note that the initial conditions (if any) apply only if the UIC option is specified on the .TRAN analysis line.

3.1.8 Coupled (Mutual) Inductors

General form:

     KXXXXXXX LYYYYYYY LZZZZZZZ VALUE

Example:

L1 3 5 10M L2 4 7 3M K L1 L2 0.81

LYYYYYYY and LZZZZZZZ are the names of the two coupled inductors, and VALUE is the coefficient of coupling, K, which must be greater than 0 and less than or equal to 1. Using the 'dot' convention, place a 'dot' on the first node of each inductor.

Ideal Transformer

SPICE has no model for an ideal transformer. An ideal tranformer is simulated using mutual inductances such that the transformer ratio N1/N2 = sqrt(L1/L2).

An ideal transformer has a coupling coefficient k=1 and very large inductances. However, Spice does not allow a coupling coefficient of k=1. The ideal transformer can be simulated in Spice by making k close to one, and the inductors L1 and L2 very large, such that wL1 and wL2 is much larger than the resistors in series with the inductors.

Make the coupling factor K close to one (ex. K=0.99999) and choose L such that wL >> the resistance seen be the inductor. The secondary circuit needs a DC connection to ground. This can be accomplished by adding a large resistor to ground or giving the primary and secondary circuits a common node.

For example, lets make wL2 >> 500 Ohm or L2> 500/(60*2pi) ; lets make L2 at least 10 times larger, ex. L2=20H. L1 can than be found from the turn ratio: L1/L2 = (N1/N2)^2. For a turn ratio of 10 this makes L1=L2x100=2000H. We make K close to 1 lets say 0.99999.

i
* Ideal transformer example * Vin defines a sinusoid of 170 V amplitude and 60 Hz. RS 2 1 10 VIN 2 0 SIN(0 170 60 0 0) L1 1 0 2000 L2 3 0 20 K L1 L2 0.99999 RL 3 0 500 .TRAN 0.2M 25M .PLOT TRAN V(2) .PLOT TRAN V(3) .END

3.1.9 Switches

Voltage Controlled Switch:

     SXXXXXXX +Nout -Nout +Nin -Nin Smodel [ON | OFF]

Current Controlled Switch:

     WYYYYYYY +Nout -Nout Vname Smodel [ON | OFF]

Examples:

   S15 3 5 8 9 SMOD

   .MODEL SMOD VSWITCH(RON = 10, VON = 0, ROFF = 100MEG)

The values of the switch parameters are RON (on - resistance), ROFF (off-resistance), VON (the control voltage for ON; default = 1V), VOFF (control voltage for OFF; default = 0V)

     s1      1 2 3  4   switch1 ON
     s2      5 6 3  0   sm2 off
     Switch1 1 2 10 0   smodel1
     w1      1 2 vclock switchmod1
     W2      3 0 vramp  sm1 ON
     wreset  5 6 vclck  lossyswitch OFF

The resistance between +Nout and -Nout will be RON when the controlling voltage (between +Nin and -Nin) is above VT + VH. The resistance will be ROFF when the controlling voltage is below VT - VH. When the controlling voltage is between VT - VH and VT + VH, the resistance will retain its prior value.

Mname refers to the switch model that is defined in another statement. The model name is mandatory while the initial conditions are optional.

For the current controlled switch, the controlling current is that through the specified voltage source. The direction of positive controlling current flow is from the positive node, through the source, to the negative node. Vname is the zero-value voltage source whose current controls the switch.

You may specify ON or OFF to indicate the initial state of the switch when the controlling voltage is in the hysteresis region.

3.1.10 Switch Model (SW/CSW)

The switch model allows an almost ideal switch to be described in SPICE. The switch is not quite ideal, in that the resistance can not change from 0 to infinity, but must always have a finite positive value. By proper selection of the on and off resistances, they can be effectively zero and infinity in comparison to other circuit elements. The parameters available are:

name parameter units default switch
VT threshold voltage Volts 0.0 S
IT threshold current Amps 0.0 W
VH hysteresis voltage Volts 0.0 S
IH hysteresis current Amps 0.0 W
RON on resistance Z 1.0 both
ROFF off resistance Z 1/GMIN* both

name	parameter	units	default	switch
VT	threshold voltage	Volts	0.0	S
IT	threshold current	Amps	0.0	W
VH	hysteresis voltage	Volts	0.0	S
IH	hysteresis current	Amps	0.0	W
RON	on resistance	Z	1.0	both
ROFF	off resistance	Z	1/GMIN*	both

*(See the .OPTIONS control line for a description of GMIN, its default value results in an off-resistance of 1.0e+12 ohms.)

The use of an ideal element that is highly nonlinear such as a switch can cause large discontinuities to occur in the circuit node voltages. A rapid change such as that associated with a switch changing state can cause numerical roundoff or tolerance problems leading to erroneous results or timestep difficulties. The user of switches can improve the situation by taking the following steps:

First, it is wise to set ideal switch impedances just high or low enough to be negligible with respect to other circuit elements. Using switch impedances that are close to "ideal" in all cases aggravates the problem of discontinuities mentioned above. Of course, when modeling real devices such as MOSFETS, the on resistance should be adjusted to a realistic level depending on the size of the device being modeled.

If a wide range of ON to OFF resistance must be used in the switches (ROFF/RON >1e+12), then the tolerance on errors allowed during transient analysis should be decreased by using the .OPTIONS control line and specifying TRTOL to be less than the default value of 7.0. When switches are placed around capacitors, then the option CHGTOL should also be reduced. Suggested values for these two options are 1.0 and 1e-16 respectively. These changes inform SPICE3 to be more careful around the switch points so that no errors are made due to the rapid change in the circuit.

3.2 VOLTAGE AND CURRENT SOURCES

3.2.1 Independent Sources

General form:

     VXXXXXXX N+ N- <<DC> DC/TRAN VALUE> <AC <ACMAG <ACPHASE>>>
     +       <DISTOF1 <F1MAG <F1PHASE>>> <DISTOF2 <F2MAG <F2PHASE>>>
     IYYYYYYY N+ N- <<DC> DC/TRAN VALUE> <AC <ACMAG <ACPHASE>>>
     +       <DISTOF1 <F1MAG <F1PHASE>>> <DISTOF2 <F2MAG <F2PHASE>>>

Examples:

     VCC 10 0 DC 6
     VIN 13 2 0.001 AC 1 SIN(0 1 1MEG)
     ISRC 23 21 AC 0.333 45.0 SFFM(0 1 10K 5 1K)
     VMEAS 12 9
     VCARRIER 1 0 DISTOF1 0.1 -90.0
     VMODULATOR 2 0 DISTOF2 0.01
     IIN1 1 5 AC 1 DISTOF1 DISTOF2 0.001

N+ and N- are the positive and negative nodes, respectively. Note that voltage sources need not be grounded. Positive current is assumed to flow from the positive node, through the source, to the negative node. A current source of positive value forces current to flow out of the N+ node, through the source, and into the N- node. Voltage sources, in addition to being used for circuit excitation, are the 'ammeters' for SPICE, that is, zero valued voltage sources may be inserted into the circuit for the purpose of measuring current. They of course have no effect on circuit operation since they represent short-circuits.

DC/TRAN is the dc and transient analysis value of the source. If the source value is zero both for dc and transient analyses, this value may be omitted. If the source value is time-invariant (e.g., a power supply), then the value may optionally be preceded by the letters DC.

ACMAG is the ac magnitude and ACPHASE is the ac phase. The source is set to this value in the ac analysis. If ACMAG is omitted following the keyword AC, a value of unity is assumed. If ACPHASE is omitted, a value of zero is assumed. If the source is not an ac small-signal input, the keyword AC and the ac values are omitted.

DISTOF1 and DISTOF2 are the keywords that specify that the independent source has distortion inputs at the frequencies F1 and F2 respectively (see the description of the .DISTO control line). The keywords may be followed by an optional magnitude and phase. The default values of the magnitude and phase are 1.0 and 0.0 respectively.

Any independent source can be assigned a time-dependent value for transient analysis. If a source is assigned a time-dependent value, the time-zero value is used for dc analysis. There are five independent source functions: pulse, exponential, sinusoidal, piece-wise linear, and single-frequency FM. If parameters other than source values are omitted or set to zero, the default values shown are assumed. (TSTEP is the printing increment and TSTOP is the final time (see the .TRAN control line for explanation)).

3.2.1.1. Pulse

General form:

     PULSE(V1 V2 TD TR TF PW PER)

Examples:

     VIN 3 0 PULSE(-1 1 2NS 2NS 2NS 50NS 100NS)

parameter default value units
V1 (initial value) V or A
V2 (pulsed value) V or A
TD (delay time) 0.0 s
TR (rise time) TSTEP s
TF (fall time) TSTEP s
PW (pulse width) TSTOP s
PER (period) TSTOP seconds

parameter	default value	units
V1 (initial value)		V or A
V2 (pulsed value)		V or A
TD (delay time)	0.0	s
TR (rise time)	TSTEP	s
TF (fall time)	TSTEP	s
PW (pulse width)	TSTOP	s
PER (period)	TSTOP	seconds

A single pulse so specified is described by the following table:

time value
0 V1
TD V1
TD+TR V2
TD+TR+PW V2
TD+TR+PW+TF V1
TSTOP V1

time	value
0	V1
TD	V1
TD+TR	V2
TD+TR+PW	V2
TD+TR+PW+TF	V1
TSTOP	V1

Intermediate points are determined by linear interpolation.

3.2.1.2 Sinusoidal

General form:

     SIN(VO VA FREQ TD THETA)

Examples:

     VIN 3 0 SIN(0 1 100MEG 1NS 1E10)

parameters default value units
VO (offset) V or A
VA (amplitude) V or A
FREQ (frequency) 1/TSTOP Hz
TD (delay) 0.0 s
THETA (damping factor) 0.0 s^-1

parameters	default value	units
VO (offset)		V or A
VA (amplitude)		V or A
FREQ (frequency)	1/TSTOP	Hz
TD (delay)	0.0	s
THETA (damping factor)	0.0	s^-1

The shape of the waveform is described by the following table:

time, t value

0 to TD VO

TD to TSTOP VO+VA.exp[-(t-TD)/THETA].sin[2π.FREQ.(t+TD)]

time, t	value
0 to TD	VO
TD to TSTOP	VO+VA.exp[-(t-TD)/THETA].sin[2π.FREQ.(t+TD)]

3.2.1.3 Exponential

General form:

     EXP(V1 V2 TD1 TAU1 TD2 TAU2)

Examples:

     VIN 3 0 EXP(-4 -1 2NS 30NS 60NS 40NS)

parameters default value units
V1 (initial value) V or A
V2 (pulsed value) V or A
TD1 (rise delay time) 0.0 s
TAU1 (rise time constant) TSTEP s
TD2 (fall delay time) TD1+TSTEP s
TAU2 (fall time constant) TSTEP s

parameters	default value	units
V1 (initial value)		V or A
V2 (pulsed value)		V or A
TD1 (rise delay time)	0.0	s
TAU1 (rise time constant)	TSTEP	s
TD2 (fall delay time)	TD1+TSTEP	s
TAU2 (fall time constant)	TSTEP	s

The shape of the waveform is described by the following table:

time, t value

0 to TD1 V1

TD1 to TD2 V1+(V2-V1).[1-exp(-(t-TD1)/TAU1)]

TD2 to TSTOP 1+(V2-V1).[1-exp(-(t-TD1)/TAU1)]+(V1-V2).[1-exp(-(t-TD2)/TAU2)]

time, t	value
0 to TD1	V1
TD1 to TD2	V1+(V2-V1).[1-exp(-(t-TD1)/TAU1)]
TD2 to TSTOP	1+(V2-V1).[1-exp(-(t-TD1)/TAU1)]+(V1-V2).[1-exp(-(t-TD2)/TAU2)]

3.2.1.4 Piece-Wise Linear

General form: PWL(T1 V1 <T2 V2 T3 V3 T4 V4 ...>)

Example:

Vg 1 2 PWL(0 0 10U 5 100U 5 110U 0)

Each pair of values (T_i, V_i) specifies that the value of the source is V_i (in Volts or Amps) at time=T_i. The value of the source at intermediate values of time is determined by using linear interpolation on the input values.

3.2.1.5 Single-Frequency FM

General form:

     SFFM(VO VA FC MDI FS)

Examples:

     V1 12 0 SFFM(0 1M 20K 5 1K)

parameter default value units

VO (offset) - volts or amps

VA (amplitude) - volts or amps

FC (carrier frequency) 1/TSTOP Hz

MDI (modulation index) - -

FS (signal frequency) 1/TSTOP Hz

parameter	default value	units
VO (offset)	-	volts or amps
VA (amplitude)	-	volts or amps
FC (carrier frequency)	1/TSTOP	Hz
MDI (modulation index)	-	-
FS (signal frequency)	1/TSTOP	Hz

The shape of the waveform is described by the following equation:

V(t)=VO+VA.sin(2πFC.t+MDI.sin[2πFS.t])

3.2.2 Linear Dependent Sources

SPICE allows circuits to contain linear dependent sources characterized by any of the four equations:

i = g.v v = e.v i = f.i v = h.i

where g, e, f, and h are constants representing transconductance, voltage gain, current gain, and transresistance, respectively.

3.2.2.1 Linear Voltage-Controlled Current Sources

General form:

     GXXXXXXX N+ N- NC+ NC- VALUE

Examples:

     G1 2 0 5 0 0.1MMHO

N+ and N- are the positive and negative nodes, respectively. Current flow is from the positive node, through the source, to the negative node. NC+ and NC- are the positive and negative controlling nodes, respectively. VALUE is the transconductance (in mhos).

3.2.2.2 Linear Voltage-Controlled Voltage Sources

General form:

     EXXXXXXX N+ N- NC+ NC- VALUE

Examples:

     E1 2 3 14 1 2.0

N+ is the positive node, and N- is the negative node. NC+ and NC- are the positive and negative controlling nodes, respectively. VALUE is the voltage gain.

3.2.2.3 Linear Current-Controlled Current Sources

General form:

     FXXXXXXX N+ N- VNAM VALUE

Examples:

     F1 13 5 VSENS 5

N+ and N- are the positive and negative nodes, respectively. Current flow is from the positive node, through the source, to the negative node. VNAM is the name of a voltage source through which the controlling current flows. The direction of positive controlling current flow is from the positive node, through the source, to the negative node of VNAM. VALUE is the

3.2.2.4 Linear Current-Controlled Voltage Sources

General form:

     HXXXXXXX N+ N- VNAM VALUE

Examples:

     HX 5 17 VZ 0.5K

N+ and N- are the positive and negative nodes, respectively. VNAM is the name of a voltage source through which the controlling current flows. The direction of positive controlling current flow is from the positive node, through the source, to the negative node of VNAM. VALUE is the transresistance (in ohms).

3.2.3 Non-linear Dependent Sources

General form:

     BXXXXXXX N+ N- <I=EXPR> <V=EXPR>

Examples:

     B1 0 1 I=cos(v(1))+sin(v(2))
     B1 0 1 V=ln(cos(log(v(1,2)^2)))-v(3)^4+v(2)^v(1)
     B1 3 4 I=17
     B1 3 4 V=exp(pi^i(vdd))

N+ is the positive node, and N- is the negative node. The values of the V and I parameters determine the voltages and currents across and through the device, respectively. If I is given then the device is a current source, and if V is given the device is a voltage source. One and only one of these parameters must be given.

[Note: The SPICE3 non-linear sources are not compatible with the poly() syntax used in SPICE2. Appendix C is included to facilitate conversion of old source. CDHW.]

The small-signal AC behavior of the nonlinear source is a linear dependent source (or sources) with a proportionality constant equal to the derivative (or derivatives) of the source at the DC operating point.

The expressions given for V and I may be any function of voltages and currents through voltage sources in the system. The following functions of real variables are defined:

abs asinh cosh sin
acos atan exp sinh
acosh atanh ln sqrt
asin cos log tan

The function "u()" is the unit step function, with a value of one for arguments greater than one and a value of zero for arguments less than zero. The function uramp(x) is the integral of the unit step: for an input x, the value is zero if x is less than zero, or if x is greater than zero the value is x. These two functions are useful in sythesizing piece-wise non-linear functions, though convergence may be adversely affected.

The following standard operators are defined:

+ - * / ^ unary -

If the argument of log(), ln(), or sqrt() becomes less than zero, the absolute value of the argument is used. If a divisor becomes zero or the argument of log() or ln() becomes zero, an error will result. Other problems may occur when the argument for a function in a partial derivative enters a region where that function is undefined.

To get time into the expression you can integrate the current from a constant current source with a capacitor and use the resulting voltage (don't forget to set the initial voltage across the capacitor). Nonlinear resistors, capacitors, and inductors may be synthesized with the nonlinear dependent source. Nonlinear resistors are obvious. Nonlinear capacitors and inductors are implemented with their linear counterparts by a change of variables implemented with the nonlinear dependent source. The following subcircuit will implement a nonlinear capacitor:


     .Subckt nlcap   pos neg
     * Bx: calculate f(input voltage)
     Bx   1    0    v = f(v(pos,neg))
     * Cx: linear capacitance
     Cx   2    0    1
     * Vx: Ammeter to measure current into the capacitor
     Vx   2    1    DC 0Volts
     * Drive the current through Cx back into the circuit
     Fx   pos  neg  Vx 1
     .ends

Non-linear inductors are similar.

3.3 TRANSMISSION LINES

[Note: The transmission line elements are not easy to use in non-trivial cases. The significance of the statement "this element models only one propagating mode" is that a length of coaxial cable has two modes (inner-shield and shield-ground), but even a simple pair of wires also has two modes (differential and common). The example file 'ltra_3.cir' shows what is required to simulate a pair of wires, and refer to [8] for the details of the calculations required. It seems that only the transmission of the voltage and current between N1 and N3 is represented by these elements, N2 and N4 are merely these nodes' respective current mirrors. CDHW.]

3.3.1 Lossless Transmission Lines

General form:

     TXXXXXXX N1 N2 N3 N4 Z0=VALUE <TD=VALUE> <F=FREQ <NL=NRMLEN>>
     +                    <IC=V1, I1, V2, I2>

Examples:

     T1 1 0 2 0 Z0=50 TD=10NS

N1 and N2 are the nodes at port 1; N3 and N4 are the nodes at port 2. Z0 is the characteristic impedance. The length of the line may be expressed in either of two forms. The transmission delay, TD, may be specified directly (as TD=10ns, for example). Alternatively, a frequency F may be given, together with NL, the normalized electrical length of the transmission line with respect to the wavelength in the line at the frequency F. If a frequency is specified but NL is omitted, 0.25 is assumed (that is, the frequency is assumed to be the quarter-wave frequency). Note that although both forms for expressing the line length are indicated as optional, one of the two must be specified.

Note that this element models only one propagating mode. If all four nodes are distinct in the actual circuit, then two modes may be excited. To simulate such a situation, two transmission-line elements are required. (see the example in Appendix A for further clarification.)

The (optional) initial condition specification consists of the voltage and current at each of the transmission line ports. Note that the initial conditions (if any) apply 'only' if the UIC option is specified on the .TRAN control line.

Note that a lossy transmission line (see below) with zero loss may be more accurate than than the lossless transmission line due to implementation details.

3.3.2 Lossy Transmission Lines

General form:

     OXXXXXXX N1 N2 N3 N4 MNAME

Examples:

     O23 1 0 2 0 LOSSYMOD
     OCONNECT 10 5 20 5 INTERCONNECT

This is a two-port convolution model for single-conductor lossy transmission lines. N1 and N2 are the nodes at port 1; N3 and N4 are the nodes at port 2. Note that a lossy transmission line with zero loss may be more accurate than than the lossless transmission line due to implementation details.

3.3.3 Lossy Transmission Line Model (LTRA)

The uniform RLC/RC/LC/RG transmission line model (referred to as the LTRA model henceforth) models a uniform constant-parameter distributed transmission line. The RC and LC cases may also be modeled using the URC and TRA models; however, the newer LTRA model is usually faster and more accurate than the others. The operation of the LTRA model is based on the convolution of the transmission line's impulse responses with its inputs (see [8]).

The LTRA model takes a number of parameters, some of which must be given and some of which are optional.

name parameter units/type default example
R resistance/length ohms/unit 0.0 0.2
L inductance/length henrys/unit 0.0 9.13e-9
G conductance/length mhos/unit 0.0 0.0
C capacitance/length farads/unit 0.0 3.65e-12
LEN length of line no default 1.0
REL breakpoint control arbitrary unit 1 0.5
ABS breakpoint control 1 5
NOSTEPLIMIT don't limit timestep to less than line delay flag not set set
NOCONTROL don't do complex timestep control flag not set set
LININTERP use linear interpolation flag not set set
MIXEDINTERP use linear when quadratic seems bad flag not set set
COMPACTREL special reltol for history compaction RELTOL 1.0e-3
COMPACTABS special abstol for history compaction ABSTOL 1.0e-9
TRUNCNR use Newton-Raphson method for timestep control flag not set set
TRUNCDONTCUT don't limit timestep to keep impulse-response errors low flag not set set

name	parameter	units/type	default	example
R	resistance/length	ohms/unit	0.0	0.2
L	inductance/length	henrys/unit	0.0	9.13e-9
G	conductance/length	mhos/unit	0.0	0.0
C	capacitance/length	farads/unit	0.0	3.65e-12
LEN	length of line		no default	1.0
REL	breakpoint control	arbitrary unit	1	0.5
ABS	breakpoint control		1	5
NOSTEPLIMIT	don't limit timestep to less than line delay	flag	not set	set
NOCONTROL	don't do complex timestep control	flag	not set	set
LININTERP	use linear interpolation	flag	not set	set
MIXEDINTERP	use linear when quadratic seems bad	flag	not set	set
COMPACTREL	special reltol for history compaction		RELTOL	1.0e-3
COMPACTABS	special abstol for history compaction		ABSTOL	1.0e-9
TRUNCNR	use Newton-Raphson method for timestep control	flag	not set	set
TRUNCDONTCUT	don't limit timestep to keep impulse-response errors low	flag	not set	set

The following types of lines have been implemented so far: RLC (uniform transmission line with series loss only), RC (uniform RC line), LC (lossless transmission line), and RG (distributed series resistance and parallel conductance only). Any other combination will yield erroneous results and should not be tried. The length LEN of the line must be specified.

NOSTEPLIMIT is a flag that will remove the default restriction of limiting time-steps to less than the line delay in the RLC case. NOCONTROL is a flag that prevents the default limiting of the time-step based on convolution error criteria in the RLC and RC cases. This speeds up simulation but may in some cases reduce the accuracy of results. LININTERP is a flag that, when specified, will use linear interpolation instead of the default quadratic interpolation for calculating delayed signals. MIXEDINTERP is a flag that, when specified, uses a metric for judging whether quadratic interpolation is not applicable and if so uses linear interpolation; otherwise it uses the default quadratic interpolation. TRUNCDONTCUT is a flag that removes the default cutting of the time-step to limit errors in the actual calculation of impulse-response related quantities. COMPACTREL and COMPACTABS are quantities that control the compaction of the past history of values stored for convolution. Larger values of these lower accuracy but usually increase simulation speed. These are to be used with the TRYTOCOMPACT option, described in the .OPTIONS section. TRUNCNR is a flag that turns on the use of Newton-Raphson iterations to determine an appropriate timestep in the timestep control routines. The default is a trial and error procedure by cutting the previous timestep in half. REL and ABS are quantities that control the setting of breakpoints.

The option most worth experimenting with for increasing the speed of simulation is REL. The default value of 1 is usually safe from the point of view of accuracy but occasionally increases computation time. A value greater than 2 eliminates all breakpoints and may be worth trying depending on the nature of the rest of the circuit, keeping in mind that it might not be safe from the viewpoint of accuracy. Breakpoints may usually be entirely eliminated if it is expected the circuit will not display sharp discontinuities. Values between 0 and 1 are usually not required but may be used for setting many breakpoints.

COMPACTREL may also be experimented with when the option TRYTOCOMPACT is specified in a .OPTIONS card. The legal range is between 0 and 1. Larger values usually decrease the accuracy of the simulation but in some cases improve speed. If TRYTOCOMPACT is not specified on a .OPTIONS card, history compaction is not attempted and accuracy is high. NOCONTROL, TRUNCDONTCUT and NOSTEPLIMIT also tend to increase speed at the expense of accuracy.

3.3.4 Uniform Distributed RC Lines (Lossy)

General form:

     UXXXXXXX N1 N2 N3 MNAME L=LEN <N=LUMPS>

Examples:

     U1 1 2 0 URCMOD L=50U
     URC2 1 12 2 UMODL l=1MIL N=6

N1 and N2 are the two element nodes the RC line connects, while N3 is the node to which the capacitances are connected. MNAME is the model name, LEN is the length of the RC line in meters. LUMPS, if specified, is the number of lumped segments to use in modeling the RC line (see the model description for the action taken if this parameter is omitted).

3.3.5 Uniform Distributed RC Model (URC)

The URC model is derived from a model proposed by L. Gertzberrg in 1974. The model is accomplished by a subcicuit type expansion of the URC line into a network of lumped RC segments with internally generated nodes. The RC segments are in a geometric progression, increasing toward the middle of the URC line, with K as a proportionality constant. The number of lumped segments used, if not specified for the URC line device, is determined by the following formula:

                                             2
                     |     R C        |(K-1)|  |
                           _ _      2
                  log|F        2 J L  |-----|  |
                       max
                     |     L L        |  K  |  |
              N =  ------------------------------
                              log K

The URC line is made up strictly of resistor and capacitor segments unless the ISPERL parameter is given a non-zero value, in which case the capacitors are replaced with reverse biased diodes with a zero-bias junction capacitance equivalent to the capacitance replaced, and with a saturation current of ISPERL amps per meter of transmission line and an optional series resistance equivalent to RSPERL ohms per meter.

# name parameter units default example area
1 K Propagation Constant - 2.0 1.2 -
2 FMAX Maximum Frequency of interest Hz 1.0 G 6.5 Meg -
3 RPERL Resistance per unit length Z m^-1 1000 10 -
4 CPERL Capacitance per unit length F m^-1 10^-15 1 pF -
5 ISPERL Saturation Current per unit length A m^-1 0 - -
6 RSPERL Diode Resistance per unit length Z m^-1 0 - -

#	name	parameter	units	default	example	area
1	K	Propagation Constant	-	2.0	1.2	-
2	FMAX	Maximum Frequency of interest	Hz	1.0 G	6.5 Meg	-
3	RPERL	Resistance per unit length	Z m^-1	1000	10	-
4	CPERL	Capacitance per unit length	F m^-1	10^-15	1 pF	-
5	ISPERL	Saturation Current per unit length	A m^-1	0	-	-
6	RSPERL	Diode Resistance per unit length	Z m^-1	0	-	-

3.4 TRANSISTORS AND DIODES

The area factor used on the diode, BJT, JFET, and MESFET devices determines the number of equivalent parallel devices of a specified model. The affected parameters are marked with an asterisk under the heading 'area' in the model descriptions below. Several geometric factors associated with the channel and the drain and source diffusions can be specified on the MOSFET device line.

Two different forms of initial conditions may be specified for some devices. The first form is included to improve the dc convergence for circuits that contain more than one stable state. If a device is specified OFF, the dc operating point is determined with the terminal voltages for that device set to zero. After convergence is obtained, the program continues to iterate to obtain the exact value for the terminal voltages. If a circuit has more than one dc stable state, the OFF option can be used to force the solution to correspond to a desired state. If a device is specified OFF when in reality the device is conducting, the program still obtains the correct solution (assuming the solutions converge) but more iterations are required since the program must independently converge to two separate solutions. The .NODESET control line serves a similar purpose as the OFF option. The .NODESET option is easier to apply and is the preferred means to aid convergence.

The second form of initial conditions are specified for use with the transient analysis. These are true 'initial conditions' as opposed to the convergence aids above. See the description of the .IC control line and the .TRAN con- trol line for a detailed explanation of initial conditions.

3.4.1 Junction Diodes

General form:

     DXXXXXXX N+ N- MNAME <AREA> <OFF> <IC=VD> <TEMP=T>

Examples:

     DBRIDGE 2 10 DIODE1
     DCLMP 3 7 DMOD 3.0 IC=0.2

N+ and N- are the positive and negative nodes, respectively. MNAME is the model name, AREA is the area factor, and OFF indicates an (optional) starting condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification using IC=VD is intended for use with the UIC option on the .TRAN control line, when a transient analysis is desired starting from other than the quiescent operating point. The (optional) TEMP value is the temperature at which this device is to operate, and overrides the temperature specification on the .OPTION control line.

3.4.2 Diode Model (D)

The dc characteristics of the diode are determined by the parameters IS and N. An ohmic resistance, RS, is included. Charge storage effects are modeled by a transit time, TT, and a nonlinear depletion layer capacitance which is determined by the parameters CJO, VJ, and M. The temperature dependence of the saturation current is defined by the parameters EG, the energy and XTI, the saturation current temperature exponent. The nominal temperature at which these parameters were measured is TNOM, which defaults to the circuit-wide value specified on the .OPTIONS control line. Reverse breakdown is modeled by an exponential increase in the reverse diode current and is determined by the parameters BV and IBV (both of which are positive numbers).

# name parameter units default example area
1 IS saturation current A 1.0e-14 1.0e-14 *
2 RS ohmic resistance Z 0 10 *
3 N emission coefficient - 1 1.0
4 TT transit-time sec 0 0.1ns
5 CJO zero-bias junction capacitance F 0 2pF *
6 VJ junction potential V 1 0.6
7 M grading coefficient - 0.5 0.5
8 EG activation energy eV 1.11 1.11 Si
0.69 Sbd
0.67 Ge
9 XTI saturation-current temp. exp - 3.0 3.0 jn
2.0 Sbd
10 KF flicker noise coefficient - 0
11 AF flicker noise exponent - 1
12 FC coefficient for forward-bias depletion capacitance formula - 0.5
13 BV reverse breakdown voltage V infinite 40.0
14 IBV current at breakdown voltage A 1.0e-3
15 TNOM parameter measurement temperature °C 27 50

#	name	parameter	units	default	example	area
1	IS	saturation current	A	1.0e-14	1.0e-14	*
2	RS	ohmic resistance	Z	0	10	*
3	N	emission coefficient	-	1	1.0
4	TT	transit-time	sec	0	0.1ns
5	CJO	zero-bias junction capacitance	F	0	2pF	*
6	VJ	junction potential	V	1	0.6
7	M	grading coefficient	-	0.5	0.5
8	EG	activation energy	eV	1.11	1.11 Si 0.69 Sbd 0.67 Ge
9	XTI	saturation-current temp. exp	-	3.0	3.0 jn 2.0 Sbd
10	KF	flicker noise coefficient	-	0
11	AF	flicker noise exponent	-	1
12	FC	coefficient for forward-bias depletion capacitance formula	-	0.5
13	BV	reverse breakdown voltage	V	infinite	40.0
14	IBV	current at breakdown voltage	A	1.0e-3
15	TNOM	parameter measurement temperature	°C	27	50

3.4.3 Bipolar Junction Transistors (BJTs)

General form:

     QXXXXXXX NC NB NE <NS> MNAME <AREA> <OFF> <IC=VBE, VCE> <TEMP=T>

Examples:

     Q23 10 24 13 QMOD IC=0.6, 5.0
     Q50A 11 26 4 20 MOD1

NC, NB, and NE are the collector, base, and emitter nodes, respectively. NS is the (optional) substrate node. If unspecified, ground is used. MNAME is the model name, AREA is the area factor, and OFF indicates an (optional) initial condition on the device for the dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification using IC=VBE, VCE is intended for use with the UIC option on the .TRAN control line, when a transient analysis is desired starting from other than the quiescent operating point. See the .IC control line description for a better way to set transient ini- tial conditions. The (optional) TEMP value is the temperature at which this device is to operate, and overrides the temperature specification on the .OPTION control line.

3.4.4 BJT Models (NPN/PNP)

The bipolar junction transistor model in SPICE is an adaptation of the integral charge control model of Gummel and Poon. This modified Gummel-Poon model extends the original model to include several effects at high bias levels. The model automatically simplifies to the simpler Ebers-Moll model when certain parameters are not specified. The parameter names used in the modified Gummel-Poon model have been chosen to be more easily understood by the program user, and to reflect better both physical and circuit design thinking.

The dc model is defined by the parameters IS, BF, NF, ISE, IKF, and NE which determine the forward current gain characteristics, IS, BR, NR, ISC, IKR, and NC which determine the reverse current gain characteristics, and VAF and VAR which determine the output conductance for forward and reverse regions. Three ohmic resistances RB, RC, and RE are included, where RB can be high current dependent. Base charge storage is modeled by forward and reverse transit times, TF and TR, the forward transit time TF being bias dependent if desired, and nonlinear depletion layer capacitances which are determined by CJE, VJE, and MJE for the B-E junction, CJC, VJC, and MJC for the B-C junction and CJS, VJS, and MJS for the C-S (Collector-Substrate) junction. The temperature dependence of the saturation current, IS, is determined by the energy-gap, EG, and the saturation current temperature exponent, XTI. Additionally base current temperature dependence is modeled by the beta temperature exponent XTB in the new model. The values specified are assumed to have been measured at the temperature TNOM, which can be specified on the .OPTIONS control line or overridden by a specification on the .MODEL line.

The BJT parameters used in the modified Gummel-Poon model are listed below. The parameter names used in earlier versions of SPICE2 are still accepted.

Modified Gummel-Poon BJT Parameters.

# name parameter units default example area
1 IS transport saturation current A 1.0e-16 1.0e-15 *
2 BF ideal maximum forward beta - 100 100
3 NF forward current emission coefficient - 1.0 1
4 VAF forward Early voltage V infinite 200
5 IKF corner for forward beta high current roll-off A infinite 0.01 *
6 ISE B-E leakage saturation current A 0 1.0e-13 *
7 NE B-E leakage emission coefficient - 1.5 2
8 BR ideal maximum reverse beta - 1 0.1
9 NR reverse current emission coefficient - 1 1
10 VAR reverse Early voltage V infinite 200
11 IKR corner for reverse beta high current roll-off A infinite 0.01 *
12 ISC B-C leakage saturation current A 0 1.0e-13 *
13 NC B-C leakage emission coefficient - 2 1.5
14 RB zero bias base resistance ohm 0 100 *
15 IRB current where base resistance falls halfway to its min value A infinite 0.1 *
16 RBM minimum base resistance at high currents ohm RB 10 *
17 RE emitter resistance ohm 0 1 *
18 RC collector resistance ohm 0 10 *
19 CJE B-E zero-bias depletion capacitance F 0 2pF *
20 VJE B-E built-in potential V 0.75 0.6
21 MJE B-E junction exponential factor - 0.33 0.33
22 TF ideal forward transit time sec 0 0.1ns
23 XTF coefficient for bias dependence of TF - 0
24 VTF voltage describing VBC dependence of TF V infinite
25 ITF high-current parameter for effect on TF A 0 *
26 PTF excess phase at freq=1.0/(TF*2PI) Hz deg 0
27 CJC B-C zero-bias depletion capacitance F 0 2pF *
28 VJC B-C built-in potential V 0.75 0.5
29 MJC B-C junction exponential factor - 0.33 0.5
30 XCJC fraction of B-C depletion capacitance connected to internal base node - 1
31 TR ideal reverse transit time sec 0 10ns
32 CJS zero-bias collector-substrate capacitance F 0 2pF *
33 VJS substrate junction built-in potential V 0.75
34 MJS substrate junction exponential factor - 0 0.5
35 XTB forward and reverse beta temperature exponent - 0
36 EG energy gap for temperature effect on IS eV 1.11
37 XTI temperature exponent for effect on IS - 3
38 KF flicker-noise coefficient - 0
39 AF flicker-noise exponent - 1
40 FC coefficient for forward-bias depletion capacitance formula - 0.5
41 TNOM Parameter measurement temperature °C 27 50

#	name	parameter	units	default	example	area
1	IS	transport saturation current	A	1.0e-16	1.0e-15	*
2	BF	ideal maximum forward beta	-	100	100
3	NF	forward current emission coefficient	-	1.0	1
4	VAF	forward Early voltage	V	infinite	200
5	IKF	corner for forward beta high current roll-off	A	infinite	0.01	*
6	ISE	B-E leakage saturation current	A	0	1.0e-13	*
7	NE	B-E leakage emission coefficient	-	1.5	2
8	BR	ideal maximum reverse beta	-	1	0.1
9	NR	reverse current emission coefficient	-	1	1
10	VAR	reverse Early voltage	V	infinite	200
11	IKR	corner for reverse beta high current roll-off	A	infinite	0.01	*
12	ISC	B-C leakage saturation current	A	0	1.0e-13	*
13	NC	B-C leakage emission coefficient	-	2	1.5
14	RB	zero bias base resistance	ohm	0	100	*
15	IRB	current where base resistance falls halfway to its min value	A	infinite	0.1	*
16	RBM	minimum base resistance at high currents	ohm	RB	10	*
17	RE	emitter resistance	ohm	0	1	*
18	RC	collector resistance	ohm	0	10	*
19	CJE	B-E zero-bias depletion capacitance	F	0	2pF	*
20	VJE	B-E built-in potential	V	0.75	0.6
21	MJE	B-E junction exponential factor	-	0.33	0.33
22	TF	ideal forward transit time	sec	0	0.1ns
23	XTF	coefficient for bias dependence of TF	-	0
24	VTF	voltage describing VBC dependence of TF	V	infinite
25	ITF	high-current parameter for effect on TF A	0			*
26	PTF	excess phase at freq=1.0/(TF*2PI) Hz	deg	0
27	CJC	B-C zero-bias depletion capacitance	F	0	2pF	*
28	VJC	B-C built-in potential	V	0.75	0.5
29	MJC	B-C junction exponential factor	-	0.33	0.5
30	XCJC	fraction of B-C depletion capacitance connected to internal base node	-	1
31	TR	ideal reverse transit time	sec	0	10ns
32	CJS	zero-bias collector-substrate capacitance	F	0	2pF	*
33	VJS	substrate junction built-in potential	V	0.75
34	MJS	substrate junction exponential factor	-	0	0.5
35	XTB	forward and reverse beta temperature exponent	-	0
36	EG	energy gap for temperature effect on IS	eV	1.11
37	XTI	temperature exponent for effect on IS	-	3
38	KF	flicker-noise coefficient	-	0
39	AF	flicker-noise exponent	-	1
40	FC	coefficient for forward-bias depletion capacitance formula	-	0.5
41	TNOM	Parameter measurement temperature	°C	27	50

3.4.5 Junction Field-Effect Transistors (JFETs)

General form:

     JXXXXXXX ND NG NS Jmodel <AREA> <OFF> <IC=VDS, VGS> <TEMP=T>

Examples:

     J1 7 2 3 JM1 OFF

ND, NG, and NS are the drain, gate, and source nodes, respectively.
Jmodel is the model name (for details, see SPICE JFET equations),
AREA is the area factor, and OFF indicates an (optional) initial condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed.
The (optional) initial condition specification, using IC=VDS, VGS is intended for use with the UIC option on the .TRAN control line, when a transient analysis is desired starting from other than the quiescent operating point. See the .IC control line for a better way to set initial conditions.
The (optional) TEMP value is the temperature at which this device is to operate, and overrides the temperature specification on the .OPTION control line.

3.4.6 JFET Models (NJF/PJF)

The JFET model is derived from the FET model of Shichman and Hodges. The dc characteristics are defined by the parameters VTO and BETA, which determine the variation of drain current with gate voltage, LAMBDA, which determines the output conductance, and IS, the saturation current of the two gate junctions. Two ohmic resistances, RD and RS, are included. Charge storage is modeled by nonlinear depletion layer capacitances for both gate junctions which vary as the -1/2 power of junction voltage and are defined by the parameters CGS, CGD, and PB.

Note that in Spice3f and later, a fitting parameter B has been added. For details, see SPICE JFET equations and [9].

# name parameter units default example area
1 VTO threshold voltage (V_TO V -2.0 -2.0
2 BETA transconductance parameter (B) A V^-2 1.0e-4 1.0e-3 *
3 LAMBDA channel-length modulation parameter (L) V^-1 0 1.0e-4
4 RD drain ohmic resistance ohm 0 100 *
5 RS source ohmic resistance ohm 0 100 *
6 CGS zero-bias G-S junction capacitance (Csub>gd) F 0 5pF *
7 CGD zero-bias G-D junction capacitance (C_gd) F 0 1pF *
8 PB gate junction potential V 1 0.6
9 IS gate junction saturation current (I_S ) A 1.0e-14 1.0e-14 *
10 B doping tail parameter - 1 1.1
11 KF flicker noise coefficient - 0
12 AF flicker noise exponent - 1
13 FC coefficient for forward-bias depletion capacitance formula - 0.5
14 TNOM parameter measurement temperature °C 27 50

#	name	parameter	units	default	example	area
1	VTO	threshold voltage (V_TO	V	-2.0	-2.0
2	BETA	transconductance parameter (B)	A V^-2	1.0e-4	1.0e-3	*
3	LAMBDA	channel-length modulation parameter (L)	V^-1	0	1.0e-4
4	RD	drain ohmic resistance	ohm	0	100	*
5	RS	source ohmic resistance	ohm	0	100	*
6	CGS	zero-bias G-S junction capacitance (Csub>gd)	F	0	5pF	*
7	CGD	zero-bias G-D junction capacitance (C_gd)	F	0	1pF	*
8	PB	gate junction potential	V	1	0.6
9	IS	gate junction saturation current (I_S )	A	1.0e-14	1.0e-14	*
10	B	doping tail parameter	-	1	1.1
11	KF	flicker noise coefficient	-	0
12	AF	flicker noise exponent	-	1
13	FC	coefficient for forward-bias depletion capacitance formula	-	0.5
14	TNOM	parameter measurement temperature	°C	27	50

3.4.7 MOSFETs

General form:

     MXXXXXXX ND NG NS NB MNAME <L=VAL> <W=VAL> <AD=VAL> <AS=VAL>
     + <PD=VAL> <PS=VAL> <NRD=VAL> <NRS=VAL> <OFF>
     + <IC=VDS, VGS, VBS> <TEMP=T>

Examples:

     M1 24 2 0 20 TYPE1
     M31 2 17 6 10 MODM L=5U W=2U
     M1 2 9 3 0 MOD1 L=10U W=5U AD=100P AS=100P PD=40U PS=40U

ND, NG, NS, and NB are the drain, gate, source, and bulk (substrate) nodes, respectively. MNAME is the model name. L and W are the channel length and width, in meters. AD and AS are the areas of the drain and source diffusions, in meter² . Note that the suffix U specifies microns (1e-6 m) and P sq-microns (1e-12 m²). If any of L, W, AD, or AS are not specified, default values are used. The use of defaults simplifies input file preparation, as well as the editing required if device geometries are to be changed. PD and PS are the perimeters of the drain and source junctions, in meters. NRD and NRS designate the equivalent number of squares of the drain and source diffusions; these values multiply the sheet resistance RSH specified on the .MODEL control line for an accurate representation of the parasitic series drain and source resistance of each transistor. PD and PS default to 0.0 while NRD and NRS to 1.0. OFF indicates an (optional) initial condition on the device for dc analysis. The (optional) initial condition specification using IC=VDS, VGS, VBS is intended for use with the UIC option on the .TRAN control line, when a transient analysis is desired starting from other than the quiescent operating point. See the .IC control line for a better and more convenient way to specify transient initial conditions. The (optional) TEMP value is the temperature at which this device is to operate, and overrides the temperature specification on the .OPTION control line. The temperature specification is ONLY valid for level 1, 2, 3, and 6 MOSFETs, not for level 4 or 5 (BSIM) devices.

3.4.8 MOSFET Models (NMOS/PMOS)

SPICE provides four MOSFET device models, which differ in the formulation of the I-V characteristic. The variable LEVEL specifies the model to be used:

LEVEL=1 Shichman-Hodges
LEVEL=2 MOS2 (as described in [1])
LEVEL=3 MOS3, a semi-empirical model (see [1])
LEVEL=4 BSIM (as described in [3])
LEVEL=5 new BSIM (BSIM2; as described in [5])
LEVEL=6 MOS6 (as described in [2])

The dc characteristics of the level 1 through level 3 MOSFETs are defined by the device parameters VTO, KP, LAMBDA, PHI and GAMMA. These parameters are computed by SPICE if process parameters (NSUB, TOX, ...) are given, but user-specified values always override. VTO is positive (negative) for enhancement mode and negative (positive) for depletion mode N-channel (P-channel) devices.

Charge storage is modeled by three constant capacitors, CGSO, CGDO, and CGBO which represent overlap capacitances, by the nonlinear thin-oxide capacitance which is distributed among the gate, source, drain, and bulk regions, and by the nonlinear depletion-layer capacitances for both substrate junctions divided into bottom and periphery, which vary as the MJ and MJSW power of junction voltage respectively, and are determined by the parameters CBD, CBS, CJ, CJSW, MJ, MJSW and PB. Charge storage effects are modeled by the piecewise linear voltages-dependent capacitance model proposed by Meyer. The thin-oxide charge-storage effects are treated slightly different for the LEVEL=1 model. These voltage-dependent capacitances are included only if TOX is specified in the input description and they are represented using Meyer's formulation.

There is some overlap among the parameters describing the junctions, e.g. the reverse current can be input either as IS (in A) or as JS (in A/m²). Whereas the first is an absolute value the second is multiplied by AD and AS to give the reverse current of the drain and source junctions respectively. This methodology has been chosen since there is no sense in relating always junction characteristics with AD and AS entered on the device line; the areas can be defaulted. The same idea applies also to the zero-bias junction capacitances CBD and CBS (in F) on one hand, and CJ (in F/m²) on the other. The parasitic drain and source series resistance can be expressed as either RD and RS (in ohms) or RSH (in ohms/sq.), the latter being multiplied by the number of squares NRD and NRS input on the device line.

A discontinuity in the MOS level 3 model with respect to the KAPPA parameter has been detected (see [10]). The supplied fix has been implemented in Spice3f2 and later. Since this fix may affect parameter fitting, the option "BADMOS3" may be set to use the old implementation (see the section on simulation variables and the ".OPTIONS" line). SPICE level 1, 2, 3 and 6 parameters:

# name parameter units default example
1 LEVEL model index - 1
2 VTO zero-bias threshold voltage (V_TO) V 0.0 1.0
3 KP transconductance parameter A V^-2 2.0e-5 3.1e-5
4 GAMMA bulk threshold parameter V^1/2 0.0 0.37
5 PHI surface potential (U) V 0.6 0.65
6 LAMBDA channel-length modulation (MOS1 and MOS2 only) (L) V^-1 0.0 0.02
7 RD drain ohmic resistance ohm 0.0 1.0
8 RS source ohmic resistance ohm 0.0 1.0
9 CBD zero-bias B-D junction capacitance F 0.0 20fF
10 CBS zero-bias B-S junction capacitance F 0.0 20fF
11 IS bulk junction saturation current (I_S) A 1.0e-14 1.0e-15
12 PB bulk junction potential V 0.8 0.87
13 CGSO gate-source overlap capacitance per meter channel width F m^-1 0.0 4.0e-11
14 CGDO gate-drain overlap capacitance per meter channel width F m^-1 0.0 4.0e-11
15 CGBO gate-bulk overlap capacitance per meter channel length F m^-1 0.0 2.0e-10
16 RSH drain and source diffusion sheet resistance ohm/[] 0.0 10.0
17 CJ zero-bias bulk junction bottom cap. per sq-meter of junction area F m-2 0.0 2.0e-4
18 MJ bulk junction bottom grading coeff. - 0.5 0.5
19 CJSW zero-bias bulk junction sidewall cap. per meter of junction perimeter F m^-1 0.0 1.0e-9
20 MJSW bulk junction sidewall grading coeff. - 0.50 (level1)
0.33 (level2,3)
21 JS bulk junction saturation current
22 TOX oxide thickness m 1.0e-7 1.0e-7
23 NSUB substrate doping cm^-3 0.0 4.0e15
24 NSS surface state density cm^-2 0.0 1.0e10
25 NFS fast surface state density cm^-2 0.0 1.0e10
26 TPG type of gate material:
+1 opp. to substrate
-1 same as substrate
0 Al gate - 1.0
27 XJ metallurgical junction depth m 0.0 1M
28 LD lateral diffusion m 0.0 0.8M
29 UO surface mobility cm² V^-1 s^-1 600 700
30 UCRIT critical field for mobility degradation (MOS2 only) V cm^-1 1.0e4 1.0e4
31 UEXP critical field exponent in mobility degradation (MOS2 only) - 0.0 0.1
32 UTRA transverse field coeff. (mobility) (deleted for MOS2) - 0.0 0.3
33 VMAX maximum drift velocity of carriers m s^-1 0.0 5.0e4
34 NEFF total channel-charge (fixed and mobile) coefficient (MOS2 only) - 1.0 5.0
35 KF flicker noise coefficient - 0.0 1.0e-26
36 AF flicker noise exponent - 1.0 1.2
37 FC coefficient for forward-bias depletion capacitance formula - 0.5
38 DELTA width effect on threshold voltage (MOS2 and MOS3) - 0.0 1.0
39 THETA mobility modulation (MOS3 only) V^-1 0.0 0.1
40 ETA static feedback (MOS3 only) - 0.0 1.0
41 KAPPA saturation field factor (MOS3 only) - 0.2 0.5
42 TNOM parameter measurement temperature °C 27 50

#	name	parameter	units	default	example
1	LEVEL	model index	-	1
2	VTO	zero-bias threshold voltage (V_TO)	V	0.0	1.0
3	KP	transconductance parameter	A V^-2	2.0e-5	3.1e-5
4	GAMMA	bulk threshold parameter	V^1/2	0.0	0.37
5	PHI	surface potential (U)	V	0.6	0.65
6	LAMBDA	channel-length modulation (MOS1 and MOS2 only) (L)	V^-1	0.0	0.02
7	RD	drain ohmic resistance	ohm	0.0	1.0
8	RS	source ohmic resistance	ohm	0.0	1.0
9	CBD	zero-bias B-D junction capacitance	F	0.0	20fF
10	CBS	zero-bias B-S junction capacitance	F	0.0	20fF
11	IS	bulk junction saturation current (I_S)	A	1.0e-14	1.0e-15
12	PB	bulk junction potential	V	0.8	0.87
13	CGSO	gate-source overlap capacitance per meter channel width	F m^-1	0.0	4.0e-11
14	CGDO	gate-drain overlap capacitance per meter channel width	F m^-1	0.0	4.0e-11
15	CGBO	gate-bulk overlap capacitance per meter channel length	F m^-1	0.0	2.0e-10
16	RSH	drain and source diffusion sheet resistance	ohm/[]	0.0	10.0
17	CJ	zero-bias bulk junction bottom cap. per sq-meter of junction area	F m-2	0.0	2.0e-4
18	MJ	bulk junction bottom grading coeff.	-	0.5	0.5
19	CJSW	zero-bias bulk junction sidewall cap. per meter of junction perimeter	F m^-1	0.0	1.0e-9
20	MJSW	bulk junction sidewall grading coeff.	-	0.50 (level1) 0.33 (level2,3)
21	JS	bulk junction saturation current
22	TOX	oxide thickness	m	1.0e-7	1.0e-7
23	NSUB	substrate doping	cm^-3	0.0	4.0e15
24	NSS	surface state density	cm^-2	0.0	1.0e10
25	NFS	fast surface state density	cm^-2	0.0	1.0e10
26	TPG	type of gate material: +1 opp. to substrate -1 same as substrate 0 Al gate	-	1.0
27	XJ	metallurgical junction depth	m	0.0	1M
28	LD	lateral diffusion	m	0.0	0.8M
29	UO	surface mobility	cm² V^-1 s^-1	600	700
30	UCRIT	critical field for mobility degradation (MOS2 only)	V cm^-1	1.0e4	1.0e4
31	UEXP	critical field exponent in mobility degradation (MOS2 only)	-	0.0	0.1
32	UTRA	transverse field coeff. (mobility) (deleted for MOS2)	-	0.0	0.3
33	VMAX	maximum drift velocity of carriers	m s^-1	0.0	5.0e4
34	NEFF	total channel-charge (fixed and mobile) coefficient (MOS2 only)	-	1.0	5.0
35	KF	flicker noise coefficient	-	0.0	1.0e-26
36	AF	flicker noise exponent	-	1.0	1.2
37	FC	coefficient for forward-bias depletion capacitance formula	-	0.5
38	DELTA	width effect on threshold voltage (MOS2 and MOS3)	-	0.0	1.0
39	THETA	mobility modulation (MOS3 only)	V^-1	0.0	0.1
40	ETA	static feedback (MOS3 only)	-	0.0	1.0
41	KAPPA	saturation field factor (MOS3 only)	-	0.2	0.5
42	TNOM	parameter measurement temperature	°C	27	50

The level 4 and level 5 (BSIM1 and BSIM2) parameters are all values obtained from process characterization, and can be generated automatically. J. Pierret [4] describes a means of generating a 'process' file, and the program Proc2Mod provided with SPICE3 converts this file into a sequence of BSIM1 ".MODEL" lines suitable for inclusion in a SPICE input file. Parameters marked below with an * in the l/w column also have corresponding parameters with a length and width dependency. For example, VFB is the basic parameter with units of volts, and LVFB and WVFB also exist and have units of volt-meter The formula

                            P            P
                             L            W
               P = P  + ---------- + ----------
                    0
                        L            W
                         effective    effective

is used to evaluate the parameter for the actual device specified with

                   L          = L      - DL
                    effective    input

and

                   W          = W      - DW
                    effective    input

Note that unlike the other models in SPICE, the BSIM model is designed for use with a process characterization system that provides all the parameters, thus there are no defaults for the parameters, and leaving one out is considered an error. For an example set of parameters and the format of a process file, see the SPICE2 implementation notes [3]. For more information on BSIM2, see reference [5].

SPICE BSIM (level 4) parameters:

name parameter units l/w
VFB flat-band voltage V *
PHI surface inversion potential V *
K1 body effect coefficient V^1/2 *
K2 drain/source depletion charge-sharing coefficient - *
ETA zero-bias drain-induced barrier-lowering coefficient - *
MUZ zero-bias mobility cm² V^-1 s^-1
DL shortening of channel µm
DW narrowing of channel µm
U0 zero-bias transverse-field mobility degradation coefficient V^-1 *
U1 zero-bias velocity saturation coefficient µm V^-1 *
X2MZ sens. of mobility to substrate bias at v=0 cm² V^-2 s^-1 *
X2E sens. of drain-induced barrier lowering effect to substrate bias V^-1 *
X3E sens. of drain-induced barrier lowering effect to drain bias at V_ds=V_dd V^-1 *
X2U0 sens. of transverse field mobility degradation effect to substrate bias V^-2 *
X2U1 sens. of velocity saturation effect to substrate bias µm V^-2 *
MUS mobility at zero substrate bias and at V_ds=V_dd cm² V^-2 s^-1
X2MS sens. of mobility to substrate bias at V_ds=V_dd cm² V^-2 s^-1 *
X3MS sens. of mobility to drain bias at V_ds=V_dd cm² V^-2 s^-1 *
X3U1 sens. of velocity saturation effect on drain bias at V_ds=V_dd µm V^-2 *
TOX gate oxide thickness µm
TEMP temperature at which parameters were measured °C
VDD measurement bias range V
CGDO gate-drain overlap capacitance per meter channel width F m^-1
CGSO gate-source overlap capacitance per meter channel width F m^-1
CGBO gate-bulk overlap capacitance per meter channel length F m^-1
XPART gate-oxide capacitance-charge model flag -
N0 zero-bias subthreshold slope coefficient - *
NB sens. of subthreshold slope to substrate bias - *
ND sens. of subthreshold slope to drain bias - *
RSH drain and source diffusion sheet resistance Z/[]
JS source drain junction current density A m^-2
PB built in potential of source drain junction V
MJ Grading coefficient of source drain junction -
PBSW built in potential of source, drain junction sidewall V
MJSW grading coefficient of source drain junction sidewall -
CJ Source drain junction capacitance per unit area F m^-2
CJSW source drain junction sidewall capacitance per unit length F m^-1
WDF source drain junction default width m
DELL Source drain junction length reduction m

name	parameter	units	l/w
VFB	flat-band voltage	V	*
PHI	surface inversion potential	V	*
K1	body effect coefficient	V^1/2	*
K2	drain/source depletion charge-sharing coefficient	-	*
ETA	zero-bias drain-induced barrier-lowering coefficient	-	*
MUZ	zero-bias mobility	cm² V^-1 s^-1
DL	shortening of channel	µm
DW	narrowing of channel	µm
U0	zero-bias transverse-field mobility degradation coefficient	V^-1	*
U1	zero-bias velocity saturation coefficient	µm V^-1	*
X2MZ	sens. of mobility to substrate bias at v=0	cm² V^-2 s^-1	*
X2E	sens. of drain-induced barrier lowering effect to substrate bias	V^-1	*
X3E	sens. of drain-induced barrier lowering effect to drain bias at V_ds=V_dd	V^-1	*
X2U0	sens. of transverse field mobility degradation effect to substrate bias	V^-2	*
X2U1	sens. of velocity saturation effect to substrate bias	µm V^-2	*
MUS	mobility at zero substrate bias and at V_ds=V_dd	cm² V^-2 s^-1
X2MS	sens. of mobility to substrate bias at V_ds=V_dd	cm² V^-2 s^-1	*
X3MS	sens. of mobility to drain bias at V_ds=V_dd	cm² V^-2 s^-1	*
X3U1	sens. of velocity saturation effect on drain bias at V_ds=V_dd	µm V^-2	*
TOX	gate oxide thickness	µm
TEMP	temperature at which parameters were measured	°C
VDD	measurement bias range	V
CGDO	gate-drain overlap capacitance per meter channel width	F m^-1
CGSO	gate-source overlap capacitance per meter channel width	F m^-1
CGBO	gate-bulk overlap capacitance per meter channel length	F m^-1
XPART	gate-oxide capacitance-charge model flag	-
N0	zero-bias subthreshold slope coefficient	-	*
NB	sens. of subthreshold slope to substrate bias	-	*
ND	sens. of subthreshold slope to drain bias	-	*
RSH	drain and source diffusion sheet resistance	Z/[]
JS	source drain junction current density	A m^-2
PB	built in potential of source drain junction	V
MJ	Grading coefficient of source drain junction	-
PBSW	built in potential of source, drain junction sidewall	V
MJSW	grading coefficient of source drain junction sidewall	-
CJ	Source drain junction capacitance per unit area	F m^-2
CJSW	source drain junction sidewall capacitance per unit length	F m^-1
WDF	source drain junction default width	m
DELL	Source drain junction length reduction	m

XPART = 0 selects a 40/60 drain/source charge partition in saturation, while XPART=1 selects a 0/100 drain/source charge partition.

ND, NG, and NS are the drain, gate, and source nodes, respectively. MNAME is the model name, AREA is the area factor, and OFF indicates an (optional) initial condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification, using IC=VDS, VGS is intended for use with the UIC option on the .TRAN control line, when a transient analysis is desired starting from other than the quiescent operating point. See the .IC control line for a better way to set initial conditions.

3.4.9 MESFETs

General form:

     ZXXXXXXX ND NG NS MNAME <AREA> <OFF> <IC=VDS, VGS>

Examples:

     Z1 7 2 3 ZM1 OFF

3.4.10 MESFET Models (NMF/PMF)

The MESFET model is derived from the GaAs FET model of Statz et al. as described in [11]. The dc characteristics are defined by the parameters VTO, B, and BETA, which determine the variation of drain current with gate voltage, ALPHA, which determines saturation voltage, and LAMBDA, which determines the output conductance. The formula are given by:

                                   3
                  2
        B (V  -V )    |    |   V  |  |                             3
            gs  T               ds                                 _
 I  = --------------- |1 - |1-A---|  |(1 + L V  )   for  0 < V   <
  d                                           ds              ds
      1 + b(V   - V ) |    |    3 |  |                             A
             gs    T
                          2
                B (V  -V )                                     3
                    gs  T                                      _
         I  = ---------------(1 + L V  )            for  V   >
          d                          ds                   ds
              1 + b(V   - V )                                  A
                     gs    T

Two ohmic resistances, RD and RS, are included. Charge storage is modeled by total gate charge as a function of gate-drain and gate-source voltages and is defined by the parameters CGS, CGD, and PB.

# name parameter units default example area
1 VTO pinch-off voltage V -2.0 -2.0
2 BETA transconductance parameter A V^-2 1.0e-4 1.0e-3 *
3 B doping tail extending parameter V^-1 0.3 0.3 *
4 ALPHA saturation voltage parameter V^-1 2 2 *
5 LAMBDA channel-length modulation parameter V^-1 0 1.0e-4
6 RD drain ohmic resistance Z 0 100 *
7 RS source ohmic resistance Z 0 100 *
8 CGS zero-bias G-S junction capacitance F 0 5pF *
9 CGD zero-bias G-D junction capacitance F 0 1pF *
10 PB gate junction potential V 1 0.6
11 KF flicker noise coefficient - 0
12 AF flicker noise exponent - 1
13 FC coefficient for forward-bias depletion capacitance formula - 0.5

#	name	parameter	units	default	example	area
1	VTO	pinch-off voltage	V	-2.0	-2.0
2	BETA	transconductance parameter	A V^-2	1.0e-4	1.0e-3	*
3	B	doping tail extending parameter	V^-1	0.3	0.3	*
4	ALPHA	saturation voltage parameter	V^-1	2	2	*
5	LAMBDA	channel-length modulation parameter	V^-1	0	1.0e-4
6	RD	drain ohmic resistance	Z	0	100	*
7	RS	source ohmic resistance	Z	0	100	*
8	CGS	zero-bias G-S junction capacitance	F	0	5pF	*
9	CGD	zero-bias G-D junction capacitance	F	0	1pF	*
10	PB	gate junction potential	V	1	0.6
11	KF	flicker noise coefficient	-	0
12	AF	flicker noise exponent	-	1
13	FC	coefficient for forward-bias depletion capacitance formula	-	0.5

0. TABLE OF CONTENTS	1. INTRODUCTION	2. CIRCUIT DESCRIPTION
3. CIRCUIT ELEMENTS AND MODELS	4. ANALYSES AND OUTPUT CONTROL	5. INTERACTIVE INTERPRETER
6. BIBLIOGRAPHY	APPENDIX A	APPENDIX B

LEVEL=1	Shichman-Hodges
LEVEL=2	MOS2 (as described in [1])
LEVEL=3	MOS3, a semi-empirical model (see [1])
LEVEL=4	BSIM (as described in [3])
LEVEL=5	new BSIM (BSIM2; as described in [5])
LEVEL=6	MOS6 (as described in [2])